{"id":"https://openalex.org/W2094797673","doi":"https://doi.org/10.1155/1995/70871","title":"A New Design Methodology for Two\u2010DimensionalLogic Arrays","display_name":"A New Design Methodology for Two\u2010DimensionalLogic Arrays","publication_year":1995,"publication_date":"1995-01-01","ids":{"openalex":"https://openalex.org/W2094797673","doi":"https://doi.org/10.1155/1995/70871","mag":"2094797673"},"language":"en","primary_location":{"id":"doi:10.1155/1995/70871","is_oa":true,"landing_page_url":"http://doi.org/10.1155/1995/70871","pdf_url":"https://downloads.hindawi.com/archive/1995/070871.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1995/070871.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014656589","display_name":"Ning Song","orcid":"https://orcid.org/0000-0003-1233-6890"},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ning Song","raw_affiliation_strings":["Lattice Semiconductor Corporation, 1820 McCarthy Blvd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corporation, 1820 McCarthy Blvd","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048693034","display_name":"Marek Perkowski","orcid":"https://orcid.org/0000-0002-0358-1176"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marek A. Perkowski","raw_affiliation_strings":["Portland State University, Department of Electrical Engineering, P.O. Box 751"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Portland State University, Department of Electrical Engineering, P.O. Box 751","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040622659","display_name":"Malgorzata Chrzanowska-Jeske","orcid":"https://orcid.org/0000-0001-5927-1751"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malgorzata Chrzanowska-Jeske","raw_affiliation_strings":["Portland State University, Department of Electrical Engineering, P.O. Box 751"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Portland State University, Department of Electrical Engineering, P.O. Box 751","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016326307","display_name":"Andisheh Sarabi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andisheh Sarabi","raw_affiliation_strings":["Viewlogic Systems, Inc., 47211 Lakeview Blvd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Viewlogic Systems, Inc., 47211 Lakeview Blvd","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5014656589"],"corresponding_institution_ids":["https://openalex.org/I116921496"],"apc_list":null,"apc_paid":null,"fwci":0.5303,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.69463902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":"3-4","first_page":"315","last_page":"332"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5610520243644714},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32493704557418823}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5610520243644714},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32493704557418823}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/1995/70871","is_oa":true,"landing_page_url":"http://doi.org/10.1155/1995/70871","pdf_url":"https://downloads.hindawi.com/archive/1995/070871.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:hindawi.com:10.1155/1995/70871","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/70871","pdf_url":null,"source":{"id":"https://openalex.org/S4306400340","display_name":"Hindawi Journal of Chemistry (Hindawi)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210126990","host_organization_name":"Hindawi (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210126990"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":{"id":"doi:10.1155/1995/70871","is_oa":true,"landing_page_url":"http://doi.org/10.1155/1995/70871","pdf_url":"https://downloads.hindawi.com/archive/1995/070871.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/14","score":0.8700000047683716,"display_name":"Life below water"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2094797673.pdf","grobid_xml":"https://content.openalex.org/works/W2094797673.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W1450614580","https://openalex.org/W1498138768","https://openalex.org/W1848132463","https://openalex.org/W1898085137","https://openalex.org/W2002864768","https://openalex.org/W2024969717","https://openalex.org/W2064298069","https://openalex.org/W2089651609","https://openalex.org/W2093670892","https://openalex.org/W2095826301","https://openalex.org/W2119414586","https://openalex.org/W2136430947","https://openalex.org/W2142823686","https://openalex.org/W2158174972","https://openalex.org/W2162494152","https://openalex.org/W2172016596","https://openalex.org/W6629632586","https://openalex.org/W6648624499","https://openalex.org/W6653807483","https://openalex.org/W6656749549","https://openalex.org/W6666591235","https://openalex.org/W6776237236"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2051487156","https://openalex.org/W2073681303","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"This":[0,29,86],"paper":[1],"introduces":[2],"a":[3,23,44,49,109,119],"new":[4],"design":[5,105],"approach":[6],"that":[7],"combines":[8],"stages":[9],"of":[10,26,59,68,123],"logic":[11,16,27],"and":[12,20,34,72,79,98,117,132],"physical":[13],"design.":[14],"The":[15,62,103],"function":[17],"is":[18,90],"synthesized":[19],"mapped":[21],"to":[22,43,84,140],"two\u2010dimensional":[24,87],"array":[25,30],"cells.":[28,127],"generalizes":[31],"PLAs,":[32],"XPLAs":[33],"cellular":[35],"Maitra":[36],"cascades.":[37],"Each":[38],"cell":[39],"can":[40,64],"be":[41],"programmed":[42],"wire,":[45],"an":[46],"inverter,":[47],"or":[48,53,115],"two\u2010input":[50],"AND,":[51],"OR":[52],"EXOR":[54],"gate":[55,63],"(with":[56],"any":[57,66],"subset":[58],"inputs":[60],"negated).":[61],"take":[65],"output":[67],"four":[69,73],"neighbor":[70,74],"cells":[71],"buses":[75],"as":[76,113],"its":[77,81],"inputs,":[78],"sends":[80],"result":[82],"back":[83],"them.":[85],"geometrical":[88],"model":[89],"well":[91],"suited":[92],"for":[93],"both":[94],"fine\u2010grain":[95],"FPGA":[96],"realization":[97],"sea\u2010of\u2010gates":[99],"custom":[100],"ASIC":[101],"layout.":[102],"comprehensive":[104],"method":[106],"starts":[107],"from":[108],"Boolean":[110],"function,":[111],"specified":[112],"SOP":[114],"ESOP,":[116],"produces":[118],"rectangularly":[120],"shaped":[121],"structure":[122],"(mostly)":[124],"locally":[125],"connected":[126],"Two":[128],"stages:":[129],"restricted":[130],"factorization,":[131],"column":[133],"folding,":[134],"are":[135],"discussed":[136],"in":[137],"more":[138],"details":[139],"illustrate":[141],"our":[142],"general":[143],"methodology.":[144]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2016-06-24T00:00:00"}