{"id":"https://openalex.org/W2149761489","doi":"https://doi.org/10.1155/1995/69526","title":"Flipping Modules to MinimizeMaximum Wire Length","display_name":"Flipping Modules to MinimizeMaximum Wire Length","publication_year":1994,"publication_date":"1994-03-28","ids":{"openalex":"https://openalex.org/W2149761489","doi":"https://doi.org/10.1155/1995/69526","mag":"2149761489"},"language":"en","primary_location":{"id":"doi:10.1155/1995/69526","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/69526","pdf_url":"https://downloads.hindawi.com/archive/1995/069526.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1995/069526.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066387235","display_name":"Kyunrak Chong","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Kyunrak Chong","raw_affiliation_strings":["Computer Science Department, Honglk University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science Department, Honglk University","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070824596","display_name":"Sartaj Sahni","orcid":"https://orcid.org/0000-0002-8129-1676"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sartaj Sahni","raw_affiliation_strings":["Computer and Information Sciences Department, University of Florida"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer and Information Sciences Department, University of Florida","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5066387235"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23092978,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":"1","first_page":"37","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9909999966621399,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9909999966621399,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9883999824523926,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9843000173568726,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/constant","display_name":"Constant (computer programming)","score":0.6418670415878296},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.5958850979804993},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.5339390635490417},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3871190845966339},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3655765652656555},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.29363903403282166},{"id":"https://openalex.org/keywords/mathematical-analysis","display_name":"Mathematical analysis","score":0.20580139756202698},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.20311832427978516}],"concepts":[{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.6418670415878296},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.5958850979804993},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.5339390635490417},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3871190845966339},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3655765652656555},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.29363903403282166},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.20580139756202698},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.20311832427978516},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/1995/69526","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/69526","pdf_url":"https://downloads.hindawi.com/archive/1995/069526.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:f33d79acfeff412da079933a826ed18d","is_oa":false,"landing_page_url":"https://doaj.org/article/f33d79acfeff412da079933a826ed18d","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 3, Iss 1, Pp 37-41 (1995)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/1995/69526","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/69526","pdf_url":"https://downloads.hindawi.com/archive/1995/069526.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2149761489.pdf","grobid_xml":"https://content.openalex.org/works/W2149761489.grobid-xml"},"referenced_works_count":9,"referenced_works":["https://openalex.org/W272982077","https://openalex.org/W1554451661","https://openalex.org/W1686033267","https://openalex.org/W1700102312","https://openalex.org/W2003160050","https://openalex.org/W2006146932","https://openalex.org/W2011039300","https://openalex.org/W2108015643","https://openalex.org/W2145550962"],"related_works":["https://openalex.org/W1979597421","https://openalex.org/W2007980826","https://openalex.org/W4245490552","https://openalex.org/W4225152035","https://openalex.org/W2061531152","https://openalex.org/W3002753104","https://openalex.org/W2077600819","https://openalex.org/W1587224694","https://openalex.org/W2911598644","https://openalex.org/W2142036596"],"abstract_inverted_index":{"We":[0],"show":[1],"that":[2],"obtaining":[3],"the":[4,11,14,55],"optimal":[5],"orientations":[6,38],"of":[7,13],"modules":[8,47],"to":[9,45],"minimize":[10],"length":[12],"longest":[15],"wire":[16],"is":[17,22,50],"NP\u2010hard.":[18],"If":[19],"each":[20],"module":[21],"permitted":[23],"only":[24],"two":[25],"possible":[26],"orientations,":[27],"this":[28],"can":[29,58],"be":[30,59],"done":[31],"in":[32,61],"linear":[33,62],"time.":[34,63],"When":[35],"all":[36],"four":[37],"are":[39,43],"permissible":[40],"and":[41],"wires":[42],"restricted":[44],"connect":[46],"whose":[48],"separation":[49],"bounded":[51],"by":[52],"some":[53],"constant,":[54],"problem":[56],"also":[57],"solved":[60]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2016-06-24T00:00:00"}
