{"id":"https://openalex.org/W2075825703","doi":"https://doi.org/10.1155/1995/26912","title":"Performance and Area Optimization of VLSISystems Using Genetic Algorithms","display_name":"Performance and Area Optimization of VLSISystems Using Genetic Algorithms","publication_year":1994,"publication_date":"1994-03-21","ids":{"openalex":"https://openalex.org/W2075825703","doi":"https://doi.org/10.1155/1995/26912","mag":"2075825703"},"language":"en","primary_location":{"id":"doi:10.1155/1995/26912","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/26912","pdf_url":"https://downloads.hindawi.com/archive/1995/026912.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1995/026912.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100382658","display_name":"Xiaodong Wang","orcid":"https://orcid.org/0000-0002-2945-9240"},"institutions":[{"id":"https://openalex.org/I92446798","display_name":"Colorado State University","ror":"https://ror.org/03k1gpj17","country_code":"US","type":"education","lineage":["https://openalex.org/I92446798"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xiao-Dong Wang","raw_affiliation_strings":["Department of Electrical Engineering, Colorado State University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Colorado State University","institution_ids":["https://openalex.org/I92446798"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090198866","display_name":"Tom Chen","orcid":"https://orcid.org/0000-0001-8037-1685"},"institutions":[{"id":"https://openalex.org/I92446798","display_name":"Colorado State University","ror":"https://ror.org/03k1gpj17","country_code":"US","type":"education","lineage":["https://openalex.org/I92446798"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom Chen","raw_affiliation_strings":["Department of Electrical Engineering, Colorado State University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Colorado State University","institution_ids":["https://openalex.org/I92446798"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100382658"],"corresponding_institution_ids":["https://openalex.org/I92446798"],"apc_list":null,"apc_paid":null,"fwci":0.5292,"has_fulltext":true,"cited_by_count":10,"citation_normalized_percentile":{"value":0.68271892,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"3","issue":"1","first_page":"43","last_page":"51"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.89834064245224},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7089687585830688},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5720953345298767},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5111730694770813},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4937456548213959},{"id":"https://openalex.org/keywords/regular-polygon","display_name":"Regular polygon","score":0.4852280616760254},{"id":"https://openalex.org/keywords/convex-optimization","display_name":"Convex optimization","score":0.4537425935268402},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4474577009677887},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3363150954246521},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.25237488746643066},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11716747283935547},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.055502116680145264}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.89834064245224},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7089687585830688},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5720953345298767},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5111730694770813},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4937456548213959},{"id":"https://openalex.org/C112680207","wikidata":"https://www.wikidata.org/wiki/Q714886","display_name":"Regular polygon","level":2,"score":0.4852280616760254},{"id":"https://openalex.org/C157972887","wikidata":"https://www.wikidata.org/wiki/Q463359","display_name":"Convex optimization","level":3,"score":0.4537425935268402},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4474577009677887},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3363150954246521},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.25237488746643066},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11716747283935547},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.055502116680145264},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/1995/26912","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/26912","pdf_url":"https://downloads.hindawi.com/archive/1995/026912.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.56.6903","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.56.6903","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.lance.colostate.edu/depts/ee/Research/vlsi/Pubs/ga.ps","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1155/1995/26912","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/26912","pdf_url":"https://downloads.hindawi.com/archive/1995/026912.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2075825703.pdf","grobid_xml":"https://content.openalex.org/works/W2075825703.grobid-xml"},"referenced_works_count":16,"referenced_works":["https://openalex.org/W1639032689","https://openalex.org/W1978921131","https://openalex.org/W2016233710","https://openalex.org/W2060393099","https://openalex.org/W2065577281","https://openalex.org/W2114888160","https://openalex.org/W2115309416","https://openalex.org/W2119562103","https://openalex.org/W2158025890","https://openalex.org/W2168525081","https://openalex.org/W2169269294","https://openalex.org/W2311046326","https://openalex.org/W3023540311","https://openalex.org/W6604012360","https://openalex.org/W6665538216","https://openalex.org/W6834562537"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W4254559750","https://openalex.org/W2998315020","https://openalex.org/W1976665945","https://openalex.org/W3016208414","https://openalex.org/W2098218272","https://openalex.org/W3153752017"],"abstract_inverted_index":{"A":[0],"new":[1],"performance":[2,103],"and":[3,27,73,104,118],"area":[4,29,76,105,120],"optimization":[5,53,90],"algorithm":[6],"for":[7,86,115,121],"complex":[8],"VLSI":[9,19,32,79],"systems":[10],"is":[11,14,34,38],"presented.":[12],"It":[13],"widely":[15],"believed":[16],"within":[17],"the":[18,23,51,71,74,98,102,112,122],"CAD":[20],"community":[21],"that":[22],"relationship":[24,69],"between":[25,70],"delay":[26,60,72,117],"silicon":[28,75,119],"of":[30,77],"a":[31,41,55,67,78],"chip":[33],"convex.":[35],"This":[36],"conclusion":[37],"based":[39,58],"on":[40],"simplified":[42],"linear":[43],"RC":[44],"model":[45,61],"to":[46,110],"predict":[47],"gate":[48],"delays.":[49],"In":[50],"proposed":[52],"algorithm,":[54],"nonlinear,":[56],"non\u2010RC":[57],"transistor":[59],"was":[62],"used":[63],"which":[64],"resulted":[65],"in":[66,101],"non\u2010convex":[68],"chip.":[80],"Genetic":[81],"algorithms":[82,100],"are":[83,108],"better":[84],"suited":[85],"discrete,":[87],"non\u2010convex,":[88],"non\u2010linear":[89],"problems":[91],"than":[92],"traditional":[93],"calculus\u2010based":[94],"algorithms.":[95],"By":[96],"using":[97],"genetic":[99],"optimization,":[106],"we":[107],"able":[109],"find":[111],"optimal":[113],"values":[114],"both":[116],"ISCAS":[123],"benchmark":[124],"circuits.":[125]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
