{"id":"https://openalex.org/W2025192014","doi":"https://doi.org/10.1155/1994/94514","title":"Temporal Logic Based Hierarchical Test Generationfor Sequential VLSI Circuits","display_name":"Temporal Logic Based Hierarchical Test Generationfor Sequential VLSI Circuits","publication_year":1993,"publication_date":"1993-01-06","ids":{"openalex":"https://openalex.org/W2025192014","doi":"https://doi.org/10.1155/1994/94514","mag":"2025192014"},"language":"en","primary_location":{"id":"doi:10.1155/1994/94514","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/94514","pdf_url":"https://downloads.hindawi.com/archive/1994/094514.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1994/094514.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074055414","display_name":"Anand V. Hudli","orcid":null},"institutions":[{"id":"https://openalex.org/I55769427","display_name":"Indiana University \u2013 Purdue University Indianapolis","ror":"https://ror.org/05gxnyn08","country_code":"US","type":"education","lineage":["https://openalex.org/I55769427","https://openalex.org/I592451"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Anand V. Hudli","raw_affiliation_strings":["Department of Computer and Information Science, Purdue School of Science, Indiana University\u2014Purdue University, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Information Science, Purdue School of Science, Indiana University\u2014Purdue University, USA","institution_ids":["https://openalex.org/I55769427"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000107443","display_name":"Raghu V. Hudli","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Raghu V. Hudli","raw_affiliation_strings":["IBM Corporation, 11400 Burnett Road, USA"],"affiliations":[{"raw_affiliation_string":"IBM Corporation, 11400 Burnett Road, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074055414"],"corresponding_institution_ids":["https://openalex.org/I55769427"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.15742129,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":"1","first_page":"69","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6792752742767334},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6422674655914307},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6204311847686768},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5898976922035217},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.578458845615387},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4948803782463074},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4354046881198883},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.42037278413772583},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4109746813774109},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38134825229644775},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.17552593350410461},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08021298050880432},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06625038385391235},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.05862247943878174}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6792752742767334},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6422674655914307},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6204311847686768},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5898976922035217},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.578458845615387},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4948803782463074},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4354046881198883},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.42037278413772583},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4109746813774109},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38134825229644775},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.17552593350410461},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08021298050880432},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06625038385391235},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.05862247943878174},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/1994/94514","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/94514","pdf_url":"https://downloads.hindawi.com/archive/1994/094514.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/1994/94514","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/94514","pdf_url":"https://downloads.hindawi.com/archive/1994/094514.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2025192014.pdf","grobid_xml":"https://content.openalex.org/works/W2025192014.grobid-xml"},"referenced_works_count":27,"referenced_works":["https://openalex.org/W157396061","https://openalex.org/W657039739","https://openalex.org/W1583437159","https://openalex.org/W1607877490","https://openalex.org/W1823755974","https://openalex.org/W1967686058","https://openalex.org/W1991369874","https://openalex.org/W1992552504","https://openalex.org/W1996682897","https://openalex.org/W2021492392","https://openalex.org/W2038569232","https://openalex.org/W2045122863","https://openalex.org/W2057956383","https://openalex.org/W2064610754","https://openalex.org/W2075920544","https://openalex.org/W2087047691","https://openalex.org/W2099164689","https://openalex.org/W2101162821","https://openalex.org/W2105975226","https://openalex.org/W2119241964","https://openalex.org/W2125618072","https://openalex.org/W2149107969","https://openalex.org/W2171065425","https://openalex.org/W2173124859","https://openalex.org/W2282097113","https://openalex.org/W4230662271","https://openalex.org/W4230769673"],"related_works":["https://openalex.org/W2386022279","https://openalex.org/W2243536805","https://openalex.org/W142017057","https://openalex.org/W1980349267","https://openalex.org/W1702800398","https://openalex.org/W1551512938","https://openalex.org/W2059930861","https://openalex.org/W2746929098","https://openalex.org/W1513105280","https://openalex.org/W2101877870"],"abstract_inverted_index":{"Test":[0],"generation":[1,53],"for":[2],"sequential":[3,23],"VLSI":[4],"circuits":[5,37],"has":[6],"remained":[7],"a":[8],"difficult":[9],"problem":[10],"to":[11,29,45],"solve.":[12],"The":[13],"difficulty":[14],"arises":[15],"because":[16],"of":[17,22,41],"reasoning":[18],"about":[19],"temporal":[20,27],"behavior":[21],"circuits.":[24,32],"We":[25],"use":[26],"logic":[28],"model":[30,36],"digital":[31],"Temporal":[33],"Logic":[34],"can":[35],"hierarchically.":[38],"A":[39,50],"set":[40],"heuristics":[42],"is":[43,55],"given":[44],"aid":[46],"during":[47],"test":[48,52],"generation.":[49],"hierarchical":[51],"algorithm":[54],"proposed.":[56]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}