{"id":"https://openalex.org/W2108886112","doi":"https://doi.org/10.1155/1994/70696","title":"Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS& BiCMOS Circuits","display_name":"Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS& BiCMOS Circuits","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W2108886112","doi":"https://doi.org/10.1155/1994/70696","mag":"2108886112"},"language":"en","primary_location":{"id":"doi:10.1155/1994/70696","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/70696","pdf_url":"https://downloads.hindawi.com/archive/1994/070696.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1994/070696.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032695064","display_name":"M.O. Esonu","orcid":null},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"M. O. Esonu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada","institution_ids":["https://openalex.org/I51768193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002571587","display_name":"D. Al-Khalili","orcid":"https://orcid.org/0000-0002-0079-8417"},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"D. Al-Khalili","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada","institution_ids":["https://openalex.org/I51768193"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017920414","display_name":"C. Rozon","orcid":null},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"C. Rozon","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada","institution_ids":["https://openalex.org/I51768193"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5032695064"],"corresponding_institution_ids":["https://openalex.org/I51768193"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.18999438,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":"4","first_page":"261","last_page":"276"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7038916349411011},{"id":"https://openalex.org/keywords/bicmos","display_name":"BiCMOS","score":0.6542301177978516},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6144285798072815},{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.5597721338272095},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5477123856544495},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5340052843093872},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5318277478218079},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.4516637623310089},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4468815326690674},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4358091354370117},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.43385615944862366},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4140089750289917},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3178156912326813},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.3108179569244385},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2928207814693451},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2895597815513611},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2489626109600067},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.22474178671836853},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.22354701161384583},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.17284244298934937}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7038916349411011},{"id":"https://openalex.org/C62427370","wikidata":"https://www.wikidata.org/wiki/Q173416","display_name":"BiCMOS","level":4,"score":0.6542301177978516},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6144285798072815},{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.5597721338272095},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5477123856544495},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5340052843093872},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5318277478218079},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.4516637623310089},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4468815326690674},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4358091354370117},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.43385615944862366},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4140089750289917},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3178156912326813},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.3108179569244385},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2928207814693451},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2895597815513611},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2489626109600067},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.22474178671836853},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.22354701161384583},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.17284244298934937},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/1994/70696","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/70696","pdf_url":"https://downloads.hindawi.com/archive/1994/070696.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/1994/70696","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1994/70696","pdf_url":"https://downloads.hindawi.com/archive/1994/070696.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2108886112.pdf","grobid_xml":"https://content.openalex.org/works/W2108886112.grobid-xml"},"referenced_works_count":7,"referenced_works":["https://openalex.org/W1759036895","https://openalex.org/W2063330999","https://openalex.org/W2079402470","https://openalex.org/W2114904900","https://openalex.org/W6642701784","https://openalex.org/W6670345985","https://openalex.org/W6684873844"],"related_works":["https://openalex.org/W2115029514","https://openalex.org/W3023943545","https://openalex.org/W1647641933","https://openalex.org/W2350960814","https://openalex.org/W1981782019","https://openalex.org/W2102956007","https://openalex.org/W2155978103","https://openalex.org/W1914094286","https://openalex.org/W2108886112","https://openalex.org/W2097503634"],"abstract_inverted_index":{"The":[0],"logic":[1],"behavior":[2],"and":[3,24,51,64,99,119],"performance":[4],"of":[5,11,22,114],"ECL":[6,46,107],"gates":[7,101,108],"under":[8],"a":[9,38,111],"set":[10,21],"defect":[12],"models":[13],"are":[14,17,74],"examined.":[15],"These":[16],"compared":[18],"with":[19,88],"equivalent":[20,55,106],"BiCMOS":[23,50,98],"CMOS":[25,54,100],"gates.":[26,56,80],"It":[27,81],"is":[28,34,82],"found":[29],"that":[30,84],"logical":[31,85,118],"fault":[32,41,86,90,95,112,121],"testing":[33,87,91,122],"inadequate":[35],"for":[36,45,49,53,97,105],"obtaining":[37],"sufficiently":[39],"high":[40],"coverage,":[42],"e.g.,":[43],"79%":[44],"versus":[47],"54%":[48],"69%":[52],"Performance":[57],"degradation":[58],"faults":[59,73],"such":[60],"as":[61,76],"delay,":[62],"current":[63],"Voltage":[65],"Transfer":[66],"Characteristics":[67],"(VTC)":[68],"or":[69],"Noise":[70],"Margin":[71],"(NM)":[72],"analyzed":[75],"applied":[77],"to":[78,109,124],"these":[79],"shown":[83],"delay":[89],"yields":[92],"the":[93],"highest":[94],"coverage":[96,113],"(around":[102],"95%).":[103],"However,":[104],"attain":[110],"around":[115],"98%,":[116],"both":[117],"NM":[120],"have":[123],"be":[125],"used.":[126]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}