{"id":"https://openalex.org/W2047359440","doi":"https://doi.org/10.1145/981066.981077","title":"Performance-driven register insertion in placement","display_name":"Performance-driven register insertion in placement","publication_year":2004,"publication_date":"2004-04-18","ids":{"openalex":"https://openalex.org/W2047359440","doi":"https://doi.org/10.1145/981066.981077","mag":"2047359440"},"language":"en","primary_location":{"id":"doi:10.1145/981066.981077","is_oa":false,"landing_page_url":"https://doi.org/10.1145/981066.981077","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 international symposium on Physical design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035692093","display_name":"Dennis K. Y. Tong","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Dennis K. Y. Tong","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin, N.T., Hong Kong","The Chinese University of Hong Kong, Shatin, N. T. Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, N.T., Hong Kong","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, N. T. Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Evangeline F. Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin, N.T., Hong Kong","The Chinese University of Hong Kong, Shatin, N. T. Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, N.T., Hong Kong","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, N. T. Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035692093"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":3.3879,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.92016239,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"53","last_page":"60"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9175340533256531},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8324503898620605},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.6764522790908813},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.658986508846283},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5725206732749939},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5618891716003418},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5313882231712341},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4819455146789551},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4507206082344055},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.43964138627052307},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4182559847831726},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.37933123111724854},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36076921224594116},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3189482092857361},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.30605411529541016},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2967455983161926},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.28814440965652466},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17662960290908813},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16186919808387756},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.10392653942108154}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9175340533256531},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8324503898620605},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.6764522790908813},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.658986508846283},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5725206732749939},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5618891716003418},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5313882231712341},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4819455146789551},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4507206082344055},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.43964138627052307},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4182559847831726},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.37933123111724854},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36076921224594116},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3189482092857361},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.30605411529541016},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2967455983161926},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.28814440965652466},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17662960290908813},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16186919808387756},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.10392653942108154},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/981066.981077","is_oa":false,"landing_page_url":"https://doi.org/10.1145/981066.981077","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2004 international symposium on Physical design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.63.7298","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.63.7298","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.cuhk.edu.hk/~fyyoung/paper/ispd04.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1966624478","https://openalex.org/W1999154739","https://openalex.org/W2030287398","https://openalex.org/W2055907896","https://openalex.org/W2087656024","https://openalex.org/W2096869104","https://openalex.org/W2129943737","https://openalex.org/W2136685778","https://openalex.org/W2142605272","https://openalex.org/W2144384460","https://openalex.org/W2148631003","https://openalex.org/W2160837527","https://openalex.org/W2161071733","https://openalex.org/W2165089524","https://openalex.org/W2169049905","https://openalex.org/W2169417961","https://openalex.org/W2169613818"],"related_works":["https://openalex.org/W2145377621","https://openalex.org/W2129192090","https://openalex.org/W2932636172","https://openalex.org/W3138092771","https://openalex.org/W4206143080","https://openalex.org/W2179342682","https://openalex.org/W4288055011","https://openalex.org/W2160837527","https://openalex.org/W4245788159","https://openalex.org/W1989297294"],"abstract_inverted_index":{"As":[0],"the":[1,7,11,52,65,84,94,110,125,140,144,161,164,171,183,188,211,219,242,257,268,272,279],"CMOS":[2,231],"technology":[3],"is":[4,116,186,190],"scaled":[5],"into":[6],"dimension":[8],"of":[9,17,67,74,96,112,127,163,205,210,247,260,267,275],"nanometer,":[10],"clock":[12,32,146,173,281],"frequencies":[13],"and":[14,100,175,202,235],"die":[15],"sizes":[16],"ICs":[18],"are":[19,38],"shown":[20,191],"to":[21,34,49,63,76,142,149,159,192,240],"be":[22,88,193],"increasing":[23],"steadily":[24],"[5].":[25],"Today,":[26],"global":[27,60,134],"wires":[28,54],"that":[29,155,252],"require":[30],"multiple":[31],"cycles":[33],"propagate":[35],"electrical":[36],"signal":[37],"prevalent":[39],"in":[40,79,90,139,182,213,265],"many":[41,150],"deep":[42],"sub-micron":[43],"designs.":[44],"Efforts":[45],"have":[46],"been":[47,104],"made":[48],"pipe":[50],"ine":[51],"long":[53],"by":[55,136],"introducing":[56],"registers":[57,78,113,138,179,261,276],"along":[58],"these":[59],"paths,":[61],"trying":[62],"reduce":[64],"impact":[66],"wire":[68,101],"delay":[69,102],"dominance":[70],"[2,":[71],"8].The":[72],"technique":[73],"retiming":[75,97,115,130],"relocate":[77],"a":[80,117,129,133,214,228,263,284],"circuit":[81,85,216],"without":[82],"affecting":[83],"functionality":[86],"can":[87,169,255],"applied":[89],"this":[91,121,203],"problem.":[92],"Though":[93],"problem":[95,126],"with":[98,197,227,244,294],"gate":[99],"has":[103],"studied":[105],"recent":[106],"y":[107],"[17,":[108],"1],":[109],"placement":[111,141],"after":[114],"new":[118],"challenge.":[119],"In":[120],"paper,":[122],"we":[123,223],"study":[124],"realizing":[128],"solution":[131],"on":[132,217,287],"netlist":[135],"inserting":[137],"achieve":[143],"target":[145,280],"period.In":[147],"contrast":[148],"previous":[151],"works":[152],"[16,":[153],"11]":[154],"performed":[156],"simple":[157],"calculations":[158],"determine":[160],"positions":[162],"registers,":[165],"our":[166,225,253],"proposed":[167],"algorithm":[168,189,226,254],"preserve":[170],"given":[172],"period":[174],"utilize":[176],"as":[177,180],"few":[178],"possible":[181],"realization.":[184],"What":[185],"more,":[187],"optimal":[194],"for":[195,262],"nets":[196,206,212],"4":[198],"or":[199],"fewer":[200],"pins":[201],"type":[204],"constitutes":[207],"over":[208],"90%":[209],"sequential":[215],"average.Using":[218],"ISCAS89":[220],"benchmark":[221],"suite,":[222],"tested":[224],"0.35":[229],"\u03bcm":[230],"standard":[232],"cell":[233],"library,":[234],"Silicon":[236],"Ensemble":[237],"was":[238],"used":[239],"layout":[241],"design":[243],"row":[245],"utilization":[246],"50%.":[248],"Experimenta":[249],"results":[250],"showed":[251],"find":[256],"best":[258],"sharing":[259],"net":[264],"most":[266],"cases,":[269],"i.e.,":[270],"using":[271],"minimum":[273],"number":[274],"while":[277],"preserving":[278],"period,":[282],"within":[283],"minute":[285],"running":[286],"an":[288],"Intel":[289],"Pentium":[290],"IV":[291],"1.5GHz":[292],"PC":[293],"512MB":[295],"RAM.":[296]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}