{"id":"https://openalex.org/W2044903484","doi":"https://doi.org/10.1145/800146.804797","title":"F/LOGIC - An interactive fault and logic simulator for digital circuits","display_name":"F/LOGIC - An interactive fault and logic simulator for digital circuits","publication_year":1976,"publication_date":"1976-01-01","ids":{"openalex":"https://openalex.org/W2044903484","doi":"https://doi.org/10.1145/800146.804797","mag":"2044903484"},"language":"en","primary_location":{"id":"doi:10.1145/800146.804797","is_oa":false,"landing_page_url":"https://doi.org/10.1145/800146.804797","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The proceedings of the thirteenth design automation conference on Design automation  - DAC '76, NO. 13","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012239947","display_name":"P. Wilcox","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"P. Wilcox","raw_affiliation_strings":[""],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081053799","display_name":"H. Rombeek","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Rombeek","raw_affiliation_strings":[""],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5012239947"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":8.1306965,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.98267327,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"68","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.7201307415962219},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.717191219329834},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.7120389938354492},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6418107151985168},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.5932528376579285},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.55569988489151},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5472020506858826},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5073782801628113},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.48753902316093445},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4750780463218689},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4431365430355072},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43981102108955383},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4158928394317627},{"id":"https://openalex.org/keywords/fault-simulator","display_name":"Fault Simulator","score":0.4103567898273468},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3560711145401001},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3550078570842743},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.17981913685798645},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17042440176010132},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.15406697988510132},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14950311183929443},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.142005056142807},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12497639656066895},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08506280183792114}],"concepts":[{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.7201307415962219},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.717191219329834},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.7120389938354492},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6418107151985168},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.5932528376579285},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.55569988489151},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5472020506858826},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5073782801628113},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.48753902316093445},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4750780463218689},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4431365430355072},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43981102108955383},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4158928394317627},{"id":"https://openalex.org/C2776365744","wikidata":"https://www.wikidata.org/wiki/Q5438149","display_name":"Fault Simulator","level":5,"score":0.4103567898273468},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3560711145401001},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3550078570842743},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.17981913685798645},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17042440176010132},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.15406697988510132},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14950311183929443},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.142005056142807},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12497639656066895},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08506280183792114},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/800146.804797","is_oa":false,"landing_page_url":"https://doi.org/10.1145/800146.804797","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The proceedings of the thirteenth design automation conference on Design automation  - DAC '76, NO. 13","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1977825116","https://openalex.org/W2029871500","https://openalex.org/W2089395542","https://openalex.org/W2129599468","https://openalex.org/W2137048602"],"related_works":["https://openalex.org/W2386022279","https://openalex.org/W2132855573","https://openalex.org/W2077986289","https://openalex.org/W2243536805","https://openalex.org/W2132306137","https://openalex.org/W2141681810","https://openalex.org/W2044903484","https://openalex.org/W2079982495","https://openalex.org/W90994724","https://openalex.org/W3141551763"],"abstract_inverted_index":{"Digital":[0],"simulators":[1,63],"are":[2],"becoming":[3],"a":[4,22,25,47,78],"standard":[5],"and":[6,36,43],"necessary":[7],"CAD":[8],"tool":[9],"in":[10],"the":[11,29,33,44],"circuit":[12],"design":[13,19],"process.":[14],"The":[15],"acceptance":[16],"of":[17,24,27,38,72,81],"this":[18],"aid":[20],"is":[21,58],"result":[23],"number":[26],"factors,":[28],"predominant":[30],"one":[31],"being":[32],"over-whelming":[34],"size":[35],"complexity":[37],"present":[39],"day":[40],"logic":[41,62],"circuits":[42,76],"requirement":[45],"that":[46,59],"complete":[48],"test":[49],"plan":[50],"be":[51,67],"developed":[52],"for":[53],"these":[54],"circuits.":[55],"Another":[56],"factor":[57],"recent":[60],"generation":[61],"have":[64],"proven":[65],"to":[66],"very":[68,74],"flexible":[69],"tools,":[70],"capable":[71],"simulating":[73],"large":[75],"with":[77],"high":[79],"degree":[80],"precision.":[82]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}