{"id":"https://openalex.org/W4412038526","doi":"https://doi.org/10.1145/3719276.3725174","title":"FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors","display_name":"FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors","publication_year":2025,"publication_date":"2025-05-28","ids":{"openalex":"https://openalex.org/W4412038526","doi":"https://doi.org/10.1145/3719276.3725174"},"language":"en","primary_location":{"id":"doi:10.1145/3719276.3725174","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3719276.3725174","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3719276.3725174","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3719276.3725174","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026686805","display_name":"Kun Qin","orcid":"https://orcid.org/0009-0007-7978-6577"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Kun Qin","raw_affiliation_strings":["Computer Architecture and Operating Systems (CAOS), CIT, Technical University of Munich, Heilbronn, Germany"],"raw_orcid":"https://orcid.org/0009-0007-7978-6577","affiliations":[{"raw_affiliation_string":"Computer Architecture and Operating Systems (CAOS), CIT, Technical University of Munich, Heilbronn, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101873158","display_name":"Xiaorang Guo","orcid":"https://orcid.org/0000-0003-1697-817X"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Xiaorang Guo","raw_affiliation_strings":["Computer Architecture and Parallel Systems (CAPS), CIT, Technical University of Munich, Garching near Munich, Germany"],"raw_orcid":"https://orcid.org/0000-0003-1697-817X","affiliations":[{"raw_affiliation_string":"Computer Architecture and Parallel Systems (CAPS), CIT, Technical University of Munich, Garching near Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045289712","display_name":"Martin Schulz","orcid":"https://orcid.org/0000-0001-9013-435X"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Martin Schulz","raw_affiliation_strings":["Computer Architecture and Parallel Systems (CAPS), CIT, Technical University of Munich, Garching near Munich, Germany"],"raw_orcid":"https://orcid.org/0000-0001-9013-435X","affiliations":[{"raw_affiliation_string":"Computer Architecture and Parallel Systems (CAPS), CIT, Technical University of Munich, Garching near Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068174103","display_name":"Carsten Trinitis","orcid":"https://orcid.org/0000-0002-6750-3652"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Carsten Trinitis","raw_affiliation_strings":["Computer Architecture and Operating Systems (CAOS), CIT, Technical University of Munich, Heilbronn, Germany and Computer Architecture and Parallel Systems (CAPS), CIT, Technical University of Munich, Garching near Munich, Germany"],"raw_orcid":"https://orcid.org/0000-0002-6750-3652","affiliations":[{"raw_affiliation_string":"Computer Architecture and Operating Systems (CAOS), CIT, Technical University of Munich, Heilbronn, Germany and Computer Architecture and Parallel Systems (CAPS), CIT, Technical University of Munich, Garching near Munich, Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12855156,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"132","last_page":"140"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7838385701179504},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7345649003982544},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5669623613357544},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5009818077087402},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47619879245758057},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44554463028907776},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.1983996033668518}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7838385701179504},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7345649003982544},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5669623613357544},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5009818077087402},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47619879245758057},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44554463028907776},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.1983996033668518}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3719276.3725174","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3719276.3725174","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3719276.3725174","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3719276.3725174","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3719276.3725174","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3719276.3725174","source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4412038526.pdf","grobid_xml":"https://content.openalex.org/works/W4412038526.grobid-xml"},"referenced_works_count":17,"referenced_works":["https://openalex.org/W2036514477","https://openalex.org/W2044605272","https://openalex.org/W2102172561","https://openalex.org/W2105991663","https://openalex.org/W2130433275","https://openalex.org/W2151591582","https://openalex.org/W2526929376","https://openalex.org/W2903605401","https://openalex.org/W2946072469","https://openalex.org/W3007003693","https://openalex.org/W4200106037","https://openalex.org/W4200634141","https://openalex.org/W4310370770","https://openalex.org/W4316659915","https://openalex.org/W4390097855","https://openalex.org/W4400113822","https://openalex.org/W4400579587"],"related_works":["https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2035206467","https://openalex.org/W2512308948","https://openalex.org/W2068921804"],"abstract_inverted_index":{"Processor":[0],"design":[1],"and":[2,20,60,100,129],"verification":[3,71,108,125],"require":[4],"a":[5,28,81,101],"synergistic":[6],"approach":[7],"that":[8,53],"combines":[9],"instruction-level":[10],"functional":[11],"simulations":[12],"with":[13,126],"precise":[14],"hardware":[15,63,114],"emulations.The":[16],"trade-off":[17],"between":[18],"speed":[19,82],"accuracy":[21],"in":[22,64],"the":[23,32,38,57,61,65,70,73,95,105,120],"instruction":[24,135],"set":[25,136],"simulation":[26],"poses":[27],"significant":[29],"challenge":[30],"to":[31,104],"efficiency":[33,131],"of":[34,40,72,83],"processor":[35,79],"verification.By":[36],"tapping":[37],"potentials":[39],"Field":[41],"Programmable":[42],"Gate":[43],"Arrays":[44],"(FPGAs),":[45],"we":[46],"propose":[47],"an":[48],"FPGA-assisted":[49],"System-on-Chip":[50],"(SoC)":[51],"platform":[52],"facilitates":[54],"cross-verification":[55],"by":[56],"embedded":[58],"CPU":[59],"synthesized":[62],"programmable":[66],"fabrics.This":[67],"method":[68],"accelerates":[69],"RISC-V":[74,134],"Instruction":[75],"Set":[76],"Architecture":[77],"(ISA)":[78],"at":[80],"5":[84],"million":[85],"instructions":[86],"per":[87],"second":[88],"(MIPS),":[89],"which":[90],"is":[91],"150x":[92],"faster":[93],"than":[94,112],"vendor-specific":[96],"tool":[97],"(Xilinx":[98],"XSim)":[99],"35x":[102],"boost":[103],"stateof-the-art":[106],"open-source":[107],"setup":[109],"(Verilator).With":[110],"less":[111],"7%":[113],"occupation":[115],"on":[116],"Zynq":[117],"7000":[118],"FPGA,":[119],"proposed":[121],"framework":[122],"enables":[123],"flexible":[124],"high":[127],"time":[128],"cost":[130],"for":[132],"exploring":[133],"architectures.":[137]},"counts_by_year":[],"updated_date":"2026-07-31T08:31:51.225901","created_date":"2025-10-10T00:00:00"}