{"id":"https://openalex.org/W2028004712","doi":"https://doi.org/10.1145/368434.368586","title":"Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer","display_name":"Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer","publication_year":2000,"publication_date":"2000-01-01","ids":{"openalex":"https://openalex.org/W2028004712","doi":"https://doi.org/10.1145/368434.368586","mag":"2028004712"},"language":"en","primary_location":{"id":"doi:10.1145/368434.368586","is_oa":true,"landing_page_url":"https://doi.org/10.1145/368434.368586","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/368434.368586","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2000 conference on Asia South Pacific design automation  - ASP-DAC '00","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/368434.368586","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010069007","display_name":"Takahiro Deguchi","orcid":null},"institutions":[{"id":"https://openalex.org/I113306721","display_name":"Hiroshima University","ror":"https://ror.org/03t78wx29","country_code":"JP","type":"education","lineage":["https://openalex.org/I113306721"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Takahiro Deguchi","raw_affiliation_strings":["Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan","institution_ids":["https://openalex.org/I113306721"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025654896","display_name":"Tetsushi Koide","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tetsushi Koide","raw_affiliation_strings":["VLSI Design and Education Center, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo 113-8656, Japan","VLSI Design and Education Center, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068636637","display_name":"Shin\u2019ichi Wakabayashi","orcid":"https://orcid.org/0000-0003-0378-7657"},"institutions":[{"id":"https://openalex.org/I113306721","display_name":"Hiroshima University","ror":"https://ror.org/03t78wx29","country_code":"JP","type":"education","lineage":["https://openalex.org/I113306721"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shin'ichi Wakabayashi","raw_affiliation_strings":["Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan","institution_ids":["https://openalex.org/I113306721"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5010069007"],"corresponding_institution_ids":["https://openalex.org/I113306721"],"apc_list":null,"apc_paid":null,"fwci":2.7558,"has_fulltext":true,"cited_by_count":11,"citation_normalized_percentile":{"value":0.89654815,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"99","last_page":"104"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7393411993980408},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6946871280670166},{"id":"https://openalex.org/keywords/citation","display_name":"Citation","score":0.6038590669631958},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5430060029029846},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5234695672988892},{"id":"https://openalex.org/keywords/library-science","display_name":"Library science","score":0.32936033606529236},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3134700655937195},{"id":"https://openalex.org/keywords/art","display_name":"Art","score":0.1567465364933014},{"id":"https://openalex.org/keywords/visual-arts","display_name":"Visual arts","score":0.12479573488235474}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7393411993980408},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6946871280670166},{"id":"https://openalex.org/C2778805511","wikidata":"https://www.wikidata.org/wiki/Q1713","display_name":"Citation","level":2,"score":0.6038590669631958},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5430060029029846},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5234695672988892},{"id":"https://openalex.org/C161191863","wikidata":"https://www.wikidata.org/wiki/Q199655","display_name":"Library science","level":1,"score":0.32936033606529236},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3134700655937195},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.1567465364933014},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.12479573488235474}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/368434.368586","is_oa":true,"landing_page_url":"https://doi.org/10.1145/368434.368586","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/368434.368586","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2000 conference on Asia South Pacific design automation  - ASP-DAC '00","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.419.9591","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.419.9591","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/compendium94-03/papers/2000/aspdac00/pdffiles/1d_3.pdf","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/368434.368586","is_oa":true,"landing_page_url":"https://doi.org/10.1145/368434.368586","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/368434.368586","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2000 conference on Asia South Pacific design automation  - ASP-DAC '00","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2028004712.pdf","grobid_xml":"https://content.openalex.org/works/W2028004712.grobid-xml"},"referenced_works_count":14,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1560792291","https://openalex.org/W1974345990","https://openalex.org/W1979569488","https://openalex.org/W1984588379","https://openalex.org/W1987786682","https://openalex.org/W2045252317","https://openalex.org/W2086760546","https://openalex.org/W2108086219","https://openalex.org/W2125690626","https://openalex.org/W2163251854","https://openalex.org/W4246849871","https://openalex.org/W4300809515","https://openalex.org/W6630623413"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2352072014","https://openalex.org/W217279133","https://openalex.org/W4205718258","https://openalex.org/W2059364457","https://openalex.org/W1989674257"],"abstract_inverted_index":{"In":[0,43],"the":[1,9,12,37,47,69,77,80],"high":[2,18,38],"performance":[3,39],"VLSI":[4],"with":[5],"multi-layer":[6,33],"layout":[7],"model,":[8],"complexity":[10],"of":[11,49,79],"global":[13,27],"routing":[14,28,34],"problem":[15,58],"becomes":[16],"much":[17],"under":[19,63],"timing":[20,64],"constraints.":[21,65],"This":[22],"paper":[23],"presents":[24],"a":[25,32,55,73],"hierarchical":[26,45],"method":[29,71,81],"based":[30],"on":[31,72],"model":[35],"for":[36],"standard":[40],"cell":[41],"layout.":[42],"each":[44],"level,":[46],"routes":[48],"nets":[50],"are":[51],"determined":[52],"by":[53],"solving":[54],"linear":[56],"programming":[57],"considering":[59],"wire-sizing":[60],"and":[61,75],"bufferinsertion":[62],"We":[66],"have":[67],"implemented":[68],"proposed":[70],"workstation":[74],"showed":[76],"effectiveness":[78],"from":[82],"experimental":[83],"results.":[84]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}