{"id":"https://openalex.org/W4376852352","doi":"https://doi.org/10.1145/3573942.3573972","title":"High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM","display_name":"High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM","publication_year":2022,"publication_date":"2022-09-23","ids":{"openalex":"https://openalex.org/W4376852352","doi":"https://doi.org/10.1145/3573942.3573972"},"language":"en","primary_location":{"id":"doi:10.1145/3573942.3573972","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3573942.3573972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 5th International Conference on Artificial Intelligence and Pattern Recognition","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100748187","display_name":"Yang Xiao-feng","orcid":"https://orcid.org/0000-0002-4150-2213"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaofeng Yang","raw_affiliation_strings":["Xi'an University of Posts and Telecommunications, China"],"raw_orcid":"https://orcid.org/0000-0002-4150-2213","affiliations":[{"raw_affiliation_string":"Xi'an University of Posts and Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111546672","display_name":"Ancheng Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ancheng Liu","raw_affiliation_strings":["Xi'an University of Posts and Telecommunications, China"],"raw_orcid":"https://orcid.org/0000-0003-2206-7655","affiliations":[{"raw_affiliation_string":"Xi'an University of Posts and Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021733435","display_name":"Jinjin Wang","orcid":"https://orcid.org/0000-0002-8216-1179"},"institutions":[{"id":"https://openalex.org/I4210136859","display_name":"Xi\u2019an University of Posts and Telecommunications","ror":"https://ror.org/04jn0td46","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210136859"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinjin Wang","raw_affiliation_strings":["Xi'an University of Posts and Telecommunications, China"],"raw_orcid":"https://orcid.org/0000-0002-8216-1179","affiliations":[{"raw_affiliation_string":"Xi'an University of Posts and Telecommunications, China","institution_ids":["https://openalex.org/I4210136859"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100748187"],"corresponding_institution_ids":["https://openalex.org/I4210136859"],"apc_list":null,"apc_paid":null,"fwci":0.1215,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46901433,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"193","last_page":"196"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9648000001907349,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9648000001907349,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13717","display_name":"Advanced Algorithms and Applications","score":0.9251000285148621,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7843934297561646},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.6851429343223572},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6556349396705627},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5293107032775879},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5022525787353516},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.45532774925231934},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.4302803874015808},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.21640020608901978},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14529573917388916}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7843934297561646},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.6851429343223572},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6556349396705627},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5293107032775879},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5022525787353516},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.45532774925231934},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.4302803874015808},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.21640020608901978},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14529573917388916}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3573942.3573972","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3573942.3573972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2022 5th International Conference on Artificial Intelligence and Pattern Recognition","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4363649224","https://openalex.org/W913418521","https://openalex.org/W2349510975","https://openalex.org/W2139640506","https://openalex.org/W2964427520","https://openalex.org/W2147511796","https://openalex.org/W2617209884","https://openalex.org/W2017378253","https://openalex.org/W2393726430","https://openalex.org/W2351416717"],"abstract_inverted_index":{"With":[0],"the":[1,7,18,32,54,113,128,136,143,159,169,213],"rapid":[2],"development":[3],"of":[4,9,20,34,42,99,123,146,181,203,222],"microelectronics":[5],"technology,":[6],"amount":[8],"data":[10,21,36,47,50,56,66,78,138,170,183,188],"information":[11],"is":[12,23,90,125,133,139,172,178],"becoming":[13,24],"larger":[14],"and":[15,17,26,38,49,64,85,88,95,109,127,135,168,174,192,196],"larger,":[16],"speed":[19,84,165],"processing":[22,67,189],"higher":[25],"higher.":[27],"In":[28],"order":[29],"to":[30,60,92,142,205],"meet":[31],"needs":[33],"today's":[35],"cache":[37,57,79,130],"solve":[39],"a":[40,69,200],"series":[41],"problems":[43],"such":[44],"as":[45,112],"unstable":[46],"transmission":[48,171],"loss":[51],"caused":[52],"by":[53],"common":[55],"technology":[58],"due":[59],"its":[61],"small":[62],"capacity":[63,87],"slow":[65],"speed,":[68],"synchronous":[70],"dynamic":[71],"random":[72],"access":[73,162],"memory":[74],"(DDR3":[75],"SDRAM)":[76],"based":[77],"design":[80,177,214],"method":[81],"with":[82,118,199],"high":[83,164],"large":[86],"multi-channel":[89,182],"proposed":[91],"achieve":[93],"fast":[94],"efficient":[96],"real-time":[97,137,219],"storage":[98],"eight-channel":[100],"video":[101,166,224],"data.":[102],"Based":[103],"on":[104],"Vivado":[105],"MIG":[106],"IP":[107],"core":[108],"Kintex-7":[110],"FPGA":[111],"control":[114,131],"core,":[115],"asynchronous":[116],"FIFO":[117],"read/write":[119,129],"bit":[120],"width":[121],"ratio":[122],"8:1":[124],"realized,":[126],"module":[132],"designed,":[134],"finally":[140],"cached":[141],"corresponding":[144],"address":[145],"DDR3":[147,150],"SDRAM.":[148],"Improved":[149],"SDRAM":[151],"bandwidth":[152],"utilization.":[153],"The":[154,176],"experimental":[155],"results":[156],"show":[157],"that":[158,212],"system":[160,221],"can":[161,215],"8-channel":[163],"data,":[167],"stable":[173],"reliable.":[175],"mainly":[179],"composed":[180],"acquisition":[184,220],"module,":[185,190],"cross-clock":[186],"domain":[187],"read":[191],"write":[193],"priority":[194],"arbitration":[195],"other":[197],"modules,":[198],"working":[201],"frequency":[202],"up":[204],"400M":[206],"Hz.":[207],"It":[208],"has":[209],"been":[210],"verified":[211],"be":[216],"used":[217],"for":[218],"space-borne":[223],"storage.":[225]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
