{"id":"https://openalex.org/W4293715596","doi":"https://doi.org/10.1145/3546591.3547532","title":"Evaluation of the Intel thread director technology on an Alder Lake processor","display_name":"Evaluation of the Intel thread director technology on an Alder Lake processor","publication_year":2022,"publication_date":"2022-08-23","ids":{"openalex":"https://openalex.org/W4293715596","doi":"https://doi.org/10.1145/3546591.3547532"},"language":"en","primary_location":{"id":"doi:10.1145/3546591.3547532","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3546591.3547532","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006978605","display_name":"Juan Carlos S\u00e1ez","orcid":"https://orcid.org/0000-0003-1343-7108"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Carlos Saez","raw_affiliation_strings":["Universidad Complutense de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Complutense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047526101","display_name":"Manuel Prieto","orcid":"https://orcid.org/0000-0003-0687-3737"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Manuel Prieto-Matias","raw_affiliation_strings":["Universidad Complutense de Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Complutense de Madrid, Spain","institution_ids":["https://openalex.org/I121748325"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I121748325"],"apc_list":null,"apc_paid":null,"fwci":3.4997,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.9331661,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"61","last_page":"67"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.7714343070983887},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7301220893859863},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.6824292540550232},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.6263076663017273},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.5798928141593933},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5716554522514343},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5658634305000305},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5184544920921326},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5181492567062378},{"id":"https://openalex.org/keywords/mobile-processor","display_name":"Mobile processor","score":0.5012280941009521},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.47118499875068665},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46596813201904297},{"id":"https://openalex.org/keywords/mobile-device","display_name":"Mobile device","score":0.4173276126384735},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3541235029697418},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13964515924453735},{"id":"https://openalex.org/keywords/mobile-technology","display_name":"Mobile technology","score":0.12326619029045105},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09045669436454773},{"id":"https://openalex.org/keywords/mobile-web","display_name":"Mobile Web","score":0.0830259919166565}],"concepts":[{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.7714343070983887},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7301220893859863},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.6824292540550232},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.6263076663017273},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.5798928141593933},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5716554522514343},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5658634305000305},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5184544920921326},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5181492567062378},{"id":"https://openalex.org/C1665295","wikidata":"https://www.wikidata.org/wiki/Q6887219","display_name":"Mobile processor","level":5,"score":0.5012280941009521},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.47118499875068665},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46596813201904297},{"id":"https://openalex.org/C186967261","wikidata":"https://www.wikidata.org/wiki/Q5082128","display_name":"Mobile device","level":2,"score":0.4173276126384735},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3541235029697418},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13964515924453735},{"id":"https://openalex.org/C60952562","wikidata":"https://www.wikidata.org/wiki/Q6887246","display_name":"Mobile technology","level":3,"score":0.12326619029045105},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09045669436454773},{"id":"https://openalex.org/C516764902","wikidata":"https://www.wikidata.org/wiki/Q1043805","display_name":"Mobile Web","level":4,"score":0.0830259919166565},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3546591.3547532","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3546591.3547532","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G822310507","display_name":null,"funder_award_id":"S2018/TCS-4423","funder_id":"https://openalex.org/F4320313831","funder_display_name":"Comunidad de Madrid"},{"id":"https://openalex.org/G8958615846","display_name":null,"funder_award_id":"RTI2018-093684-B-I00","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"}],"funders":[{"id":"https://openalex.org/F4320313831","display_name":"Comunidad de Madrid","ror":null},{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W313974161","https://openalex.org/W1971910541","https://openalex.org/W2002671355","https://openalex.org/W2042556025","https://openalex.org/W2133990480","https://openalex.org/W2512608889","https://openalex.org/W2564949789","https://openalex.org/W2754640706","https://openalex.org/W2803785720","https://openalex.org/W2996353500","https://openalex.org/W2998965290","https://openalex.org/W3004300886","https://openalex.org/W3137978547","https://openalex.org/W4205116588","https://openalex.org/W4230405802","https://openalex.org/W4232955467","https://openalex.org/W4235679005","https://openalex.org/W4244731318","https://openalex.org/W4247264372"],"related_works":["https://openalex.org/W1547865754","https://openalex.org/W2276000909","https://openalex.org/W4250432526","https://openalex.org/W2101536355","https://openalex.org/W2171175484","https://openalex.org/W2940837694","https://openalex.org/W2085872434","https://openalex.org/W2026084820","https://openalex.org/W2562747857","https://openalex.org/W4308095153"],"abstract_inverted_index":{"Asymmetric":[0],"multicore":[1],"processors":[2],"(AMPs)":[3],"combine":[4],"high-performance":[5],"big":[6],"cores":[7],"with":[8],"more":[9],"energy-efficient":[10],"small":[11],"cores,":[12],"all":[13],"exposing":[14],"a":[15],"shared":[16],"instruction-set":[17],"architecture":[18],"but":[19],"different":[20],"features,":[21],"such":[22],"as":[23],"clock":[24],"frequency":[25],"or":[26,69],"microarchitecture.":[27],"In":[28],"the":[29,39,58,62,70,94],"last":[30],"decade,":[31],"most":[32],"commercial":[33],"AMP":[34,83],"products":[35,52],"have":[36],"mainly":[37],"targetted":[38],"embedded":[40],"and":[41],"mobile":[42,59],"domains.":[43],"Today,":[44],"major":[45],"hardware":[46],"players":[47],"are":[48,77],"releasing":[49],"new":[50,82],"AMP-based":[51],"that":[53],"aim":[54],"to":[55,93],"move":[56],"beyond":[57],"niche,":[60],"towards":[61],"desktop/server":[63],"segments.":[64],"The":[65],"Apple":[66],"M1":[67],"SoC":[68],"recent":[71],"Intel":[72],"Alder":[73],"Lake":[74],"processor":[75],"family":[76],"clear":[78],"examples":[79],"of":[80],"these":[81],"systems.":[84],"Despite":[85],"their":[86],"energy-efficiency":[87],"benefits,":[88],"AMPs":[89],"pose":[90],"significant":[91],"challenges":[92],"operating":[95],"system":[96],"scheduler.":[97]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":6}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}