{"id":"https://openalex.org/W2909382341","doi":"https://doi.org/10.1145/3287624.3287683","title":"IR-ATA","display_name":"IR-ATA","publication_year":2019,"publication_date":"2019-01-18","ids":{"openalex":"https://openalex.org/W2909382341","doi":"https://doi.org/10.1145/3287624.3287683","mag":"2909382341"},"language":"en","primary_location":{"id":"doi:10.1145/3287624.3287683","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3287624.3287683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055723008","display_name":"Ashkan Vakil","orcid":"https://orcid.org/0000-0002-5029-8330"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ashkan Vakil","raw_affiliation_strings":["George Mason University"],"affiliations":[{"raw_affiliation_string":"George Mason University","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047382437","display_name":"Houman Homayoun","orcid":"https://orcid.org/0000-0001-8904-4699"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Houman Homayoun","raw_affiliation_strings":["George Mason University"],"affiliations":[{"raw_affiliation_string":"George Mason University","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060036961","display_name":"Avesta Sasan","orcid":"https://orcid.org/0000-0002-4052-8075"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Avesta Sasan","raw_affiliation_strings":["George Mason University"],"affiliations":[{"raw_affiliation_string":"George Mason University","institution_ids":["https://openalex.org/I162714631"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5055723008"],"corresponding_institution_ids":["https://openalex.org/I162714631"],"apc_list":null,"apc_paid":null,"fwci":0.5961,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.67273113,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"152","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6442548036575317},{"id":"https://openalex.org/keywords/voltage-drop","display_name":"Voltage drop","score":0.6024974584579468},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.5838525295257568},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5816154479980469},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5739755034446716},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.5629019141197205},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5626163482666016},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5589007139205933},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5381172299385071},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4817228615283966},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4776812195777893},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.44416800141334534},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41736191511154175},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.310965895652771},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27290546894073486},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2232273519039154},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08259075880050659}],"concepts":[{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6442548036575317},{"id":"https://openalex.org/C82178898","wikidata":"https://www.wikidata.org/wiki/Q166839","display_name":"Voltage drop","level":3,"score":0.6024974584579468},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.5838525295257568},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5816154479980469},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5739755034446716},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.5629019141197205},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5626163482666016},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5589007139205933},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5381172299385071},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4817228615283966},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4776812195777893},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.44416800141334534},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41736191511154175},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.310965895652771},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27290546894073486},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2232273519039154},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08259075880050659},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3287624.3287683","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3287624.3287683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2034793671","https://openalex.org/W2101512735","https://openalex.org/W2115314588","https://openalex.org/W2120463846","https://openalex.org/W2130464226","https://openalex.org/W2134067926","https://openalex.org/W2134509461","https://openalex.org/W2139197213","https://openalex.org/W2160055399","https://openalex.org/W2163527337","https://openalex.org/W2168159483","https://openalex.org/W2340344720","https://openalex.org/W2744818718","https://openalex.org/W2798443351","https://openalex.org/W2798840702","https://openalex.org/W2963001922","https://openalex.org/W3105554950","https://openalex.org/W4233028387","https://openalex.org/W4236986999","https://openalex.org/W4386858270"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2743305891","https://openalex.org/W2070693700","https://openalex.org/W2908947570","https://openalex.org/W4391382037","https://openalex.org/W2374651972","https://openalex.org/W4309227549","https://openalex.org/W1899580521","https://openalex.org/W2097839191"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"IR-ATA,":[3],"a":[4,54,86,131],"novel":[5],"flow":[6],"for":[7,35,57,93,99,123,161],"modeling":[8,58],"the":[9,16,30,37,91,104,112,115,125,143,152],"timing":[10,20,67,101,117,144],"impact":[11,145],"of":[12,22,80,130,146,163],"IR":[13,38,94],"drop":[14,39,95],"during":[15],"physical":[17,147,153],"design":[18,105],"and":[19,32,40,59,76,96,128],"closure":[21],"an":[23],"ASIC":[24],"chip.":[25],"We":[26],"first":[27],"illustrate":[28,135],"how":[29,136],"current":[31],"conventional":[33],"mechanism":[34],"budgeting":[36],"voltage":[41,62,81,97],"noise":[42,98],"(by":[43],"using":[44],"hard":[45],"margins)":[46],"lead":[47],"to":[48,141,155],"sub-optimal":[49],"design.":[50,132],"Consequently,":[51],"we":[52,134],"propose":[53],"new":[55],"approach":[56],"margining":[60,89],"against":[61],"noise,":[63],"such":[64,85],"that":[65,119,158],"each":[66],"path":[68,87],"is":[69],"margined":[70],"based":[71,88],"on":[72],"its":[73,77],"own":[74,78],"topology":[75],"view":[79],"noise.":[82],"By":[83],"having":[84],"mechanism,":[90],"margins":[92],"most":[100],"paths":[102],"in":[103,111],"are":[106],"safely":[107],"relaxed.":[108],"The":[109],"reduction":[110],"margin":[113],"increases":[114],"available":[116],"slack":[118],"could":[120,138],"be":[121,139],"used":[122,140],"improving":[124],"power,":[126],"performance,":[127],"area":[129],"Finally,":[133],"IR-ATA":[137],"track":[142],"or":[148],"PDN":[149],"changes,":[150],"allowing":[151],"designers":[154],"explore":[156],"tradeoffs":[157],"were":[159],"previously,":[160],"lack":[162],"methodology,":[164],"not":[165],"possible.":[166]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2019-01-25T00:00:00"}