{"id":"https://openalex.org/W2888391482","doi":"https://doi.org/10.1145/3229082","title":"Folded Circuit Synthesis","display_name":"Folded Circuit Synthesis","publication_year":2018,"publication_date":"2018-08-22","ids":{"openalex":"https://openalex.org/W2888391482","doi":"https://doi.org/10.1145/3229082","mag":"2888391482"},"language":"en","primary_location":{"id":"doi:10.1145/3229082","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3229082","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031562748","display_name":"Inhak Han","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Inhak Han","raw_affiliation_strings":["KAIST, Daejeon, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KAIST, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["KAIST, Daejeon, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KAIST, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157485424"],"apc_list":null,"apc_paid":null,"fwci":0.1263,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46937255,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":"5","first_page":"1","last_page":"21"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7619059681892395},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7610139846801758},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6145632266998291},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5866329073905945},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5852041840553284},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5058352947235107},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4979743957519531},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.47670644521713257},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.44615769386291504},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.44192278385162354},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37140268087387085},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.34472474455833435},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.21571066975593567},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1442289650440216},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0866369903087616},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0810522735118866}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7619059681892395},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7610139846801758},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6145632266998291},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5866329073905945},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5852041840553284},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5058352947235107},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4979743957519531},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47670644521713257},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.44615769386291504},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.44192278385162354},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37140268087387085},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.34472474455833435},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.21571066975593567},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1442289650440216},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0866369903087616},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0810522735118866},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3229082","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3229082","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1612810659","https://openalex.org/W2011039300","https://openalex.org/W2024223745","https://openalex.org/W2027101033","https://openalex.org/W2036887642","https://openalex.org/W2039473024","https://openalex.org/W2069560114","https://openalex.org/W2089300475","https://openalex.org/W2100465945","https://openalex.org/W2113092930","https://openalex.org/W2117880765","https://openalex.org/W2125850227","https://openalex.org/W2128957415","https://openalex.org/W2142766971","https://openalex.org/W2154502576","https://openalex.org/W3141112769"],"related_works":["https://openalex.org/W2384756109","https://openalex.org/W2237508561","https://openalex.org/W2369485957","https://openalex.org/W2535130387","https://openalex.org/W1592424226","https://openalex.org/W2166402441","https://openalex.org/W2090956884","https://openalex.org/W4242994585","https://openalex.org/W2886316835","https://openalex.org/W1829289753"],"abstract_inverted_index":{"The":[0],"area":[1,83],"required":[2],"by":[3,17,31],"combinational":[4,61],"logic":[5,62],"of":[6,24,47,84],"a":[7,60],"sequential":[8],"circuit":[9,82],"based":[10],"on":[11,38],"standard":[12],"flip-flops":[13,36],"can":[14,27],"be":[15,29],"reduced":[16],"identifying":[18],"subcircuits":[19,26],"that":[20],"are":[21],"identical.":[22],"Pairs":[23],"matching":[25],"then":[28],"replaced":[30],"circuits":[32,76],"in":[33,81],"which":[34],"dual-edge-triggered":[35],"operate":[37],"multiplexed":[39],"data":[40],"at":[41],"the":[42,48,56,65],"rising":[43],"and":[44],"falling":[45],"edges":[46],"clock":[49],"signal.":[50],"We":[51],"show":[52],"how":[53],"to":[54,63],"modify":[55],"Boolean":[57],"network":[58],"describing":[59],"increase":[64],"opportunities":[66],"for":[67],"folding,":[68],"without":[69],"affecting":[70],"its":[71],"function.":[72],"Experiments":[73],"with":[74],"benchmark":[75],"achieved":[77],"an":[78],"average":[79],"reduction":[80],"18%.":[85]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
