{"id":"https://openalex.org/W2623597682","doi":"https://doi.org/10.1145/3069593.3069614","title":"Hot Row Identification of DRAM Memory in a Multicore System","display_name":"Hot Row Identification of DRAM Memory in a Multicore System","publication_year":2017,"publication_date":"2017-03-22","ids":{"openalex":"https://openalex.org/W2623597682","doi":"https://doi.org/10.1145/3069593.3069614","mag":"2623597682"},"language":"en","primary_location":{"id":"doi:10.1145/3069593.3069614","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3069593.3069614","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on High Performance Compilation, Computing and Communications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103769026","display_name":"Tao Xi","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xi Tao","raw_affiliation_strings":["Department of Computer Information Science Engineering, University of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Computer Information Science Engineering, University of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062103245","display_name":"Q. Zeng","orcid":"https://orcid.org/0000-0001-9060-0357"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qi Zeng","raw_affiliation_strings":["Department of Computer Information Science Engineering, University of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Computer Information Science Engineering, University of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110277378","display_name":"Jih-Kwon Peir","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jih-Kwon Peir","raw_affiliation_strings":["Department of Computer Information Science Engineering, University of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Computer Information Science Engineering, University of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103769026"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.06934932,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"71","last_page":"75"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.8246906399726868},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8226027488708496},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7555429935455322},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.730568528175354},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5987189412117004},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.5819196701049805},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5635393261909485},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4172000586986542},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4109882712364197},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3749980926513672},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29747912287712097},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.23116934299468994},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.18699690699577332},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.1048586368560791}],"concepts":[{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.8246906399726868},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8226027488708496},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7555429935455322},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.730568528175354},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5987189412117004},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.5819196701049805},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5635393261909485},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4172000586986542},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4109882712364197},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3749980926513672},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29747912287712097},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.23116934299468994},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18699690699577332},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.1048586368560791},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3069593.3069614","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3069593.3069614","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on High Performance Compilation, Computing and Communications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1498525413","https://openalex.org/W1504046403","https://openalex.org/W1979866689","https://openalex.org/W2026517532","https://openalex.org/W2054319838","https://openalex.org/W2056200836","https://openalex.org/W2120829734","https://openalex.org/W2128962653","https://openalex.org/W2138146350","https://openalex.org/W2162639668","https://openalex.org/W2166263440","https://openalex.org/W3145545382"],"related_works":["https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2800412005","https://openalex.org/W4386903460","https://openalex.org/W1989117745","https://openalex.org/W2130233920","https://openalex.org/W2080843961"],"abstract_inverted_index":{"Access":[0],"locality":[1],"in":[2,9,32,39],"single-core":[3],"system":[4,11],"is":[5,26],"not":[6],"easily":[7],"observed":[8],"multicore":[10],"due":[12],"to":[13,22,28,55,68,73],"interleaved":[14],"requests":[15,50,67],"from":[16],"different":[17,52,74],"cores.":[18],"Requests":[19],"that":[20],"come":[21],"DRAM-based":[23],"main":[24],"memory":[25,58,63],"mapped":[27],"a":[29,47],"specific":[30],"bank":[31],"DRAM":[33,42],"and":[34],"accessed":[35],"through":[36],"row":[37,71],"buffer":[38],"the":[40,56,69],"bank.":[41],"row-buffer":[43],"conflicts":[44],"occur":[45],"when":[46],"sequence":[48],"of":[49],"on":[51],"rows":[53],"goes":[54],"same":[57,70],"bank,":[59],"causing":[60],"much":[61],"higher":[62],"access":[64],"latency":[65],"than":[66],"or":[72],"banks.":[75]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}