{"id":"https://openalex.org/W2626552439","doi":"https://doi.org/10.1145/3061639.3062183","title":"A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits","display_name":"A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits","publication_year":2017,"publication_date":"2017-06-13","ids":{"openalex":"https://openalex.org/W2626552439","doi":"https://doi.org/10.1145/3061639.3062183","mag":"2626552439"},"language":"en","primary_location":{"id":"doi:10.1145/3061639.3062183","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062183","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089015378","display_name":"Niranjan Kulkarni","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Niranjan Kulkarni","raw_affiliation_strings":["School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe AZ"],"affiliations":[{"raw_affiliation_string":"School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe AZ","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074963592","display_name":"Aykut Dengi","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aykut Dengi","raw_affiliation_strings":["School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe AZ"],"affiliations":[{"raw_affiliation_string":"School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe AZ","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030130819","display_name":"Sarma Vrudhula","orcid":"https://orcid.org/0000-0001-9278-2959"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarma Vrudhula","raw_affiliation_strings":["School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe AZ"],"affiliations":[{"raw_affiliation_string":"School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe AZ","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5089015378"],"corresponding_institution_ids":["https://openalex.org/I55732556"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.06068689,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8523918986320496},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.8468371629714966},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.816077470779419},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.7130290269851685},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6747312545776367},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6632481813430786},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6566314101219177},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5755241513252258},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5678603053092957},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5241382718086243},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5041259527206421},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4839530289173126},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4578269124031067},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.43924039602279663},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4158353805541992},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.415637344121933},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.41513383388519287},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3977229595184326},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33042415976524353},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2147861123085022},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19663149118423462},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1390916109085083},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09412044286727905},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07298743724822998}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8523918986320496},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.8468371629714966},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.816077470779419},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.7130290269851685},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6747312545776367},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6632481813430786},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6566314101219177},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5755241513252258},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5678603053092957},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5241382718086243},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5041259527206421},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4839530289173126},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4578269124031067},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.43924039602279663},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4158353805541992},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.415637344121933},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.41513383388519287},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3977229595184326},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33042415976524353},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2147861123085022},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19663149118423462},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1390916109085083},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09412044286727905},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07298743724822998},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3061639.3062183","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062183","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7200000286102295,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1511469799","https://openalex.org/W1518236483","https://openalex.org/W1582800210","https://openalex.org/W1875554762","https://openalex.org/W2011778848","https://openalex.org/W2027357691","https://openalex.org/W2099989103","https://openalex.org/W2120390801","https://openalex.org/W2266612535","https://openalex.org/W2345076121"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W3006003651","https://openalex.org/W2127892766","https://openalex.org/W2144282137"],"abstract_inverted_index":{"A":[0],"new":[1,60,114],"method":[2,15,51],"for":[3,45],"reducing":[4,121],"power":[5,174],"and":[6,100,109,123,152,175,181],"area":[7,122,151,176],"of":[8,26,59,89,120,158,161,184],"standard":[9],"cell":[10],"ASICs":[11],"is":[12,16,34,68,85,94,144,166],"described.":[13],"The":[14,50],"based":[17],"on":[18,134,179],"deliberately":[19],"introducing":[20,162],"clock":[21,31,43,97],"skew":[22,130],"without":[23],"the":[24,30,57,107,113,118,135,140,156],"use":[25],"extra":[27,132],"buffers":[28],"in":[29,78,112,173],"network.":[32],"This":[33],"done":[35],"by":[36,146],"having":[37],"some":[38],"flipflops,":[39,47,142],"called":[40,48],"sources,":[41],"generate":[42],"signals":[44],"other":[46,98],"targets.":[49],"involves":[52],"two":[53],"key":[54],"features:":[55],"(1)":[56],"design":[58],"differential":[61],"flipflop,":[62,76],"referred":[63],"to":[64,71,96,149],"as":[65],"KVFF,":[66],"that":[67,84,105,138],"functionally":[69],"identical":[70],"a":[72,86],"master-slave":[73],"edge-triggered":[74],"D":[75],"but":[77],"addition,":[79,155],"produces":[80],"an":[81,102],"completion":[82],"signal":[83],"skewed":[87],"version":[88],"its":[90],"input":[91],"clock,":[92],"which":[93,143],"used":[95],"flipflops;":[99],"(2)":[101],"efficient":[103],"algorithm":[104],"identifies":[106],"sources":[108],"targets":[110],"involved":[111],"clocking":[115],"scheme,":[116],"with":[117],"objective":[119],"power.":[124,153],"These":[125],"are":[126,177],"reduced":[127],"because":[128],"deliberate":[129],"introduces":[131],"slack":[133],"logic":[136],"cones":[137],"feed":[139],"target":[141],"exploited":[145],"synthesis":[147],"tools":[148],"reduce":[150],"In":[154],"overhead":[157],"conventional":[159],"methods":[160],"skew,":[163],"e.g.":[164],"buffers,":[165],"eliminated.":[167],"Using":[168],"commercial":[169],"tools,":[170],"significant":[171],"improvements":[172],"shown":[178],"placed":[180],"routed":[182],"netlists":[183],"several":[185],"circuits.":[186]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}