{"id":"https://openalex.org/W2049880113","doi":"https://doi.org/10.1145/2684746.2689087","title":"Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs","display_name":"Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W2049880113","doi":"https://doi.org/10.1145/2684746.2689087","mag":"2049880113"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689087","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689087","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043377990","display_name":"Joshua S. Monson","orcid":null},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joshua S. Monson","raw_affiliation_strings":["Brigham Young University, Provo, UT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018034033","display_name":"Brad Hutchings","orcid":"https://orcid.org/0000-0002-2991-0230"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brad L. Hutchings","raw_affiliation_strings":["Brigham Young University, Provo, UT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I100005738"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"5","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7987979650497437},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7932854890823364},{"id":"https://openalex.org/keywords/visibility","display_name":"Visibility","score":0.777227520942688},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7312055230140686},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.720847487449646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5577455759048462},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.546557605266571},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4725995659828186},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4314115345478058},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32110774517059326},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14614030718803406}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7987979650497437},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7932854890823364},{"id":"https://openalex.org/C123403432","wikidata":"https://www.wikidata.org/wiki/Q654068","display_name":"Visibility","level":2,"score":0.777227520942688},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7312055230140686},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.720847487449646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5577455759048462},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.546557605266571},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4725995659828186},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4314115345478058},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32110774517059326},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14614030718803406},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2684746.2689087","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689087","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W745443168","https://openalex.org/W1978408137","https://openalex.org/W2009541799","https://openalex.org/W2072073269","https://openalex.org/W2072367650","https://openalex.org/W2090808187","https://openalex.org/W2141919235","https://openalex.org/W2156499539","https://openalex.org/W2162113220","https://openalex.org/W2174390426","https://openalex.org/W4251859441"],"related_works":["https://openalex.org/W4321442002","https://openalex.org/W2015265939","https://openalex.org/W2284072287","https://openalex.org/W2611067230","https://openalex.org/W2392812199","https://openalex.org/W2993910401","https://openalex.org/W2612099726","https://openalex.org/W2160632767","https://openalex.org/W1924077319","https://openalex.org/W2619340758"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3],"method":[4,54],"for":[5],"extending":[6],"source-level":[7,18,23],"visibility":[8,24,58],"into":[9,28],"the":[10,41,50,65,71],"RTL":[11],"of":[12,35,52,70],"an":[13],"HLS-generated":[14],"design":[15],"using":[16],"automated":[17],"transformations.":[19],"Using":[20],"our":[21,53],"method,":[22],"can":[25],"be":[26,61],"extended":[27],"co-simulation,":[29],"in-system":[30],"simulation,":[31],"and":[32],"hardware":[33],"execution":[34],"any":[36],"HLS":[37],"tool":[38],"that":[39],"provides":[40],"ability":[42],"to":[43,60],"infer":[44],"top-level":[45],"ports.":[46],"Experimental":[47],"results":[48],"show":[49],"feasibility":[51],"in":[55],"situations":[56],"where":[57],"needs":[59],"added":[62],"without":[63],"modifying":[64],"timing,":[66],"latency,":[67],"or":[68],"throughput":[69],"design.":[72]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":5}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}