{"id":"https://openalex.org/W2112238627","doi":"https://doi.org/10.1145/2483028.2483130","title":"Physical design exploration of 3D tree-based FPGA architecture","display_name":"Physical design exploration of 3D tree-based FPGA architecture","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2112238627","doi":"https://doi.org/10.1145/2483028.2483130","mag":"2112238627"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483130","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal.science/hal-00873292","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044271464","display_name":"Vinod Pangracious","orcid":"https://orcid.org/0000-0002-4240-6610"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Vinod Pangracious","raw_affiliation_strings":["UPMC, Sorbonne University, Paris, France"],"affiliations":[{"raw_affiliation_string":"UPMC, Sorbonne University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040282351","display_name":"Emna Amouri","orcid":"https://orcid.org/0000-0003-2107-3658"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Emna Amouri","raw_affiliation_strings":["UPMC, Sorbonne University, Paris, France"],"affiliations":[{"raw_affiliation_string":"UPMC, Sorbonne University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["UPMC, Sorbonne University, Paris, France"],"affiliations":[{"raw_affiliation_string":"UPMC, Sorbonne University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zied Marrakchi","raw_affiliation_strings":["FlexRas Technologies, Paris, France"],"affiliations":[{"raw_affiliation_string":"FlexRas Technologies, Paris, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5044271464"],"corresponding_institution_ids":["https://openalex.org/I39804081"],"apc_list":null,"apc_paid":null,"fwci":0.2404,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.6341989,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"335","last_page":"336"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7785335779190063},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.7093680500984192},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6740052103996277},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6398544907569885},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.6212608814239502},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5990277528762817},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4879745841026306},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40102607011795044},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3482056260108948},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21745029091835022},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10383173823356628},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07578375935554504}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7785335779190063},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.7093680500984192},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6740052103996277},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6398544907569885},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.6212608814239502},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5990277528762817},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4879745841026306},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40102607011795044},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3482056260108948},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21745029091835022},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10383173823356628},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07578375935554504},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2483028.2483130","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00873292v1","is_oa":true,"landing_page_url":"https://hal.science/hal-00873292","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"GLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, May 2013, Paris, France. pp.335-336, ⟨10.1145/2483028.2483130⟩","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-00873292v1","is_oa":true,"landing_page_url":"https://hal.science/hal-00873292","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"GLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, May 2013, Paris, France. pp.335-336, ⟨10.1145/2483028.2483130⟩","raw_type":"Conference papers"},"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1481987700","https://openalex.org/W1581887721","https://openalex.org/W1967049292","https://openalex.org/W2047199967","https://openalex.org/W2111427553","https://openalex.org/W2139109474","https://openalex.org/W2139637699","https://openalex.org/W2152446494"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2082487009","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"An":[0],"innovative":[1],"3D":[2,47],"physical":[3,48],"design":[4,49],"exploration":[5,50],"methodology":[6,51],"for":[7],"Tree-based":[8,18],"FPGA":[9,19],"architecture":[10],"is":[11],"presented":[12],"in":[13,25,74],"this":[14,75],"paper.":[15,76],"In":[16],"a":[17,26,41,59],"architecture,":[20],"the":[21,30,64],"interconnects":[22,66],"are":[23],"arranged":[24],"multidimensional":[27],"network":[28,44],"with":[29],"logic":[31],"unites":[32],"and":[33],"switch":[34],"blocks":[35],"placed":[36],"at":[37],"different":[38],"levels,":[39],"using":[40,58],"Butterfly-Fat":[42],"Tree":[43,65],"topology.":[45],"A":[46],"leverage":[52],"on":[53],"Through":[54],"Silicon":[55],"Via":[56],"(TSVs)":[57],"horizontal":[60],"break-point":[61],"to":[62],"re-distribute":[63],"into":[67],"multiple":[68],"stacked":[69],"active":[70],"silicon":[71],"layers":[72],"proposed":[73]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}