{"id":"https://openalex.org/W2098633867","doi":"https://doi.org/10.1145/2400682.2400717","title":"SCIN-cache","display_name":"SCIN-cache","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2098633867","doi":"https://doi.org/10.1145/2400682.2400717","mag":"2098633867"},"language":"en","primary_location":{"id":"doi:10.1145/2400682.2400717","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2400682.2400717","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2400682.2400717","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/2400682.2400717","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074808832","display_name":"Anurag Negi","orcid":null},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Anurag Negi","raw_affiliation_strings":["Chalmers University of Technology, Gothenburg, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082812702","display_name":"Rub\u00e9n Titos-Gil","orcid":"https://orcid.org/0000-0002-9790-5011"},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Ruben Titos-Gil","raw_affiliation_strings":["Chalmers University of Technology, Gothenburg, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I66862912"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17736387,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":"4","first_page":"1","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9060629606246948},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.723371148109436},{"id":"https://openalex.org/keywords/speculative-multithreading","display_name":"Speculative multithreading","score":0.6052594184875488},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5135364532470703},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.5123814344406128},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4978668689727783},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.47756677865982056},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4687894284725189},{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.44476330280303955},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42636266350746155},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3251383304595947},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.2994561791419983},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29695940017700195},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.23262783885002136},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1815406084060669}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9060629606246948},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.723371148109436},{"id":"https://openalex.org/C15296174","wikidata":"https://www.wikidata.org/wiki/Q7575343","display_name":"Speculative multithreading","level":4,"score":0.6052594184875488},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5135364532470703},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.5123814344406128},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4978668689727783},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.47756677865982056},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4687894284725189},{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.44476330280303955},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42636266350746155},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3251383304595947},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.2994561791419983},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29695940017700195},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.23262783885002136},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1815406084060669},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2400682.2400717","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2400682.2400717","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2400682.2400717","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},{"id":"pmh:oai:research.chalmers.se:174344","is_oa":false,"landing_page_url":"https://research.chalmers.se/en/publication/174344","pdf_url":null,"source":{"id":"https://openalex.org/S4306402469","display_name":"Chalmers Research (Chalmers University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I66862912","host_organization_name":"Chalmers University of Technology","host_organization_lineage":["https://openalex.org/I66862912"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null}],"best_oa_location":{"id":"doi:10.1145/2400682.2400717","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2400682.2400717","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2400682.2400717","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[{"id":"https://openalex.org/G4463753044","display_name":"Mjukvaruabstraktioner f\u00f6r heterogena multiprocessorer","funder_award_id":"RIT10-0033","funder_id":"https://openalex.org/F4320320940","funder_display_name":"Stiftelsen f\u00f6r\u00a0Strategisk Forskning"}],"funders":[{"id":"https://openalex.org/F4320320940","display_name":"Stiftelsen f\u00f6r\u00a0Strategisk Forskning","ror":"https://ror.org/044wr7g58"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2098633867.pdf","grobid_xml":"https://content.openalex.org/works/W2098633867.grobid-xml"},"referenced_works_count":35,"referenced_works":["https://openalex.org/W1525227808","https://openalex.org/W1828727480","https://openalex.org/W1969885689","https://openalex.org/W2014271889","https://openalex.org/W2029479717","https://openalex.org/W2037630885","https://openalex.org/W2040490564","https://openalex.org/W2057769886","https://openalex.org/W2099537990","https://openalex.org/W2101545021","https://openalex.org/W2105900173","https://openalex.org/W2107150212","https://openalex.org/W2110710544","https://openalex.org/W2111825130","https://openalex.org/W2113751407","https://openalex.org/W2114240372","https://openalex.org/W2114251233","https://openalex.org/W2118329536","https://openalex.org/W2120142006","https://openalex.org/W2120635877","https://openalex.org/W2123437221","https://openalex.org/W2124651507","https://openalex.org/W2131867938","https://openalex.org/W2136674263","https://openalex.org/W2138476373","https://openalex.org/W2152484003","https://openalex.org/W2163654949","https://openalex.org/W2164264749","https://openalex.org/W2164686985","https://openalex.org/W2170582961","https://openalex.org/W2171607039","https://openalex.org/W2911386821","https://openalex.org/W3145491929","https://openalex.org/W3147996988","https://openalex.org/W4234703016"],"related_works":["https://openalex.org/W1796231360","https://openalex.org/W1571368810","https://openalex.org/W2379400621","https://openalex.org/W2611544471","https://openalex.org/W2506225776","https://openalex.org/W1616582327","https://openalex.org/W1484089092","https://openalex.org/W1598062406","https://openalex.org/W2110723369","https://openalex.org/W2098633867"],"abstract_inverted_index":{"This":[0],"article":[1],"describes":[2],"cache":[3,26],"designs":[4,63],"for":[5,47],"efficiently":[6],"supporting":[7],"speculative":[8,25,43],"techniques":[9],"like":[10],"transactional":[11],"memory":[12],"on":[13,34],"chip":[14],"multiprocessors":[15],"with":[16,72,80],"multithreaded":[17],"cores.":[18],"On-demand":[19],"allocation":[20],"and":[21,42,52],"prompt":[22],"freeing":[23],"of":[24,45],"space":[27],"in":[28,76],"the":[29,32,62],"design":[30,54,70],"reduces":[31],"burden":[33],"nonspeculative":[35],"execution.":[36],"Quick":[37],"access":[38],"to":[39,56],"both":[40],"clean":[41],"versions":[44],"data":[46],"multiple":[48],"contexts":[49],"provides":[50],"flexibility":[51],"greater":[53],"freedom":[55],"HTM":[57,69],"architects.":[58],"Performance":[59],"analysis":[60],"shows":[61],"stand":[64],"up":[65],"well":[66],"against":[67],"other":[68],"proposals,":[71],"potential":[73],"performance":[74],"gains":[75],"high":[77],"contention":[78],"applications":[79],"small":[81],"transactions.":[82]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2016-06-24T00:00:00"}