{"id":"https://openalex.org/W1973765113","doi":"https://doi.org/10.1145/2370816.2370821","title":"PGCapping","display_name":"PGCapping","publication_year":2012,"publication_date":"2012-09-19","ids":{"openalex":"https://openalex.org/W1973765113","doi":"https://doi.org/10.1145/2370816.2370821","mag":"1973765113"},"language":"en","primary_location":{"id":"doi:10.1145/2370816.2370821","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2370816.2370821","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058648644","display_name":"Kai Ma","orcid":"https://orcid.org/0000-0003-3517-5620"},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kai Ma","raw_affiliation_strings":["the Ohio State University, Columbus, USA","Department of Electrical and Computer Engineering, the Ohio State University, Columbus, 43210, USA"],"affiliations":[{"raw_affiliation_string":"the Ohio State University, Columbus, USA","institution_ids":["https://openalex.org/I52357470"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, the Ohio State University, Columbus, 43210, USA","institution_ids":["https://openalex.org/I52357470"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100658019","display_name":"Xiaorui Wang","orcid":"https://orcid.org/0000-0001-9633-1418"},"institutions":[{"id":"https://openalex.org/I52357470","display_name":"The Ohio State University","ror":"https://ror.org/00rs6vg23","country_code":"US","type":"education","lineage":["https://openalex.org/I52357470"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaorui Wang","raw_affiliation_strings":["the Ohio State University, Columbus, USA","Department of Electrical and Computer Engineering, the Ohio State University, Columbus, 43210, USA"],"affiliations":[{"raw_affiliation_string":"the Ohio State University, Columbus, USA","institution_ids":["https://openalex.org/I52357470"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, the Ohio State University, Columbus, 43210, USA","institution_ids":["https://openalex.org/I52357470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5058648644"],"corresponding_institution_ids":["https://openalex.org/I52357470"],"apc_list":null,"apc_paid":null,"fwci":6.3813,"has_fulltext":false,"cited_by_count":75,"citation_normalized_percentile":{"value":0.9681469,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"13","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.916129469871521},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7402606010437012},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.7239474058151245},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6593901515007019},{"id":"https://openalex.org/keywords/testbed","display_name":"Testbed","score":0.658022940158844},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6105632185935974},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5485509037971497},{"id":"https://openalex.org/keywords/power-management","display_name":"Power management","score":0.5020067691802979},{"id":"https://openalex.org/keywords/pooling","display_name":"Pooling","score":0.4662190079689026},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4514528512954712},{"id":"https://openalex.org/keywords/decoupling","display_name":"Decoupling (probability)","score":0.4509628415107727},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.4488424062728882},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4439144432544708},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2584928274154663},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1795109212398529},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.16769811511039734},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16757753491401672},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14576348662376404},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11792251467704773}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.916129469871521},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7402606010437012},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.7239474058151245},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6593901515007019},{"id":"https://openalex.org/C31395832","wikidata":"https://www.wikidata.org/wiki/Q1318674","display_name":"Testbed","level":2,"score":0.658022940158844},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6105632185935974},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5485509037971497},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.5020067691802979},{"id":"https://openalex.org/C70437156","wikidata":"https://www.wikidata.org/wiki/Q7228652","display_name":"Pooling","level":2,"score":0.4662190079689026},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4514528512954712},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.4509628415107727},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.4488424062728882},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4439144432544708},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2584928274154663},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1795109212398529},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.16769811511039734},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16757753491401672},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14576348662376404},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11792251467704773},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2370816.2370821","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2370816.2370821","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.699999988079071}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320337345","display_name":"Office of Naval Research","ror":"https://ror.org/00rk2pe57"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1513016807","https://openalex.org/W1517866176","https://openalex.org/W1964622779","https://openalex.org/W1975295215","https://openalex.org/W1989874002","https://openalex.org/W2005442397","https://openalex.org/W2028573862","https://openalex.org/W2036548030","https://openalex.org/W2038337218","https://openalex.org/W2048153962","https://openalex.org/W2096910408","https://openalex.org/W2099865945","https://openalex.org/W2100484677","https://openalex.org/W2100948980","https://openalex.org/W2101360724","https://openalex.org/W2109546606","https://openalex.org/W2112806194","https://openalex.org/W2116175063","https://openalex.org/W2117299787","https://openalex.org/W2129542184","https://openalex.org/W2132101661","https://openalex.org/W2132301251","https://openalex.org/W2133521202","https://openalex.org/W2134026160","https://openalex.org/W2134782496","https://openalex.org/W2137374876","https://openalex.org/W2141721356","https://openalex.org/W2144034023","https://openalex.org/W2144614141","https://openalex.org/W2145901239","https://openalex.org/W2149813938","https://openalex.org/W2149959321","https://openalex.org/W2150440358","https://openalex.org/W2154169726","https://openalex.org/W2156756912","https://openalex.org/W2157189715","https://openalex.org/W2161625020","https://openalex.org/W2162082972","https://openalex.org/W2167678606","https://openalex.org/W2171762108","https://openalex.org/W4240567521"],"related_works":["https://openalex.org/W2259094912","https://openalex.org/W1987649265","https://openalex.org/W2066983888","https://openalex.org/W2371329481","https://openalex.org/W2034989381","https://openalex.org/W2147614189","https://openalex.org/W2560557593","https://openalex.org/W2137671689","https://openalex.org/W2121397687","https://openalex.org/W2048188644"],"abstract_inverted_index":{"Optimizing":[0],"the":[1,37,56,71,77,94,101,125,150,185,189,200,212,264],"performance":[2,222],"of":[3,17,96,124,127,237],"a":[4,9,15,46,84,134,207,234,253],"chip":[5],"multiprocessor":[6],"(CMP)":[7],"within":[8],"power":[10,51,78,139,145,151,157,196,226,260],"cap":[11],"has":[12],"recently":[13],"received":[14],"lot":[16],"attention.":[18],"However,":[19,65,170],"most":[20],"existing":[21],"solutions":[22],"rely":[23],"solely":[24],"on":[25,69,75,163,206,259,269],"DVFS,":[26],"which":[27],"is":[28,154],"anticipated":[29],"to":[30,55,93,121,137,198,217],"have":[31],"only":[32],"limited":[33],"actuation":[34],"ranges":[35],"in":[36,45,83,188],"future.":[38],"Power":[39],"gating":[40,79,140,197],"shuts":[41],"down":[42],"idling":[43],"cores":[44,57,165,176],"CMP,":[47],"such":[48],"that":[49,58,104,153,166,211,252],"more":[50,119],"can":[52,114,262],"be":[53,115],"shifted":[54],"run":[59,167],"applications":[60],"for":[61,143,229],"better":[62,219],"CMP":[63,144,265],"performance.":[64],"current":[66],"preliminary":[67],"studies":[68],"integrating":[70],"two":[72,102],"knobs":[73,103],"focus":[74],"deciding":[76],"and":[80,118,182,239],"DVFS":[81,142],"levels":[82],"tightly":[85],"coupled":[86],"fashion,":[87],"with":[88,107,141,248],"much":[89,178],"less":[90,116],"attention":[91],"given":[92],"direction":[95],"decoupled":[97,135],"designs.":[98],"By":[99],"decoupling":[100],"may":[105,173],"interfere":[106],"each":[108],"other,":[109],"individual":[110],"knob":[111],"management":[112],"algorithms":[113],"complex":[117],"efficient":[120],"take":[122],"advantage":[123],"characteristics":[126],"different":[128],"knobs.":[129],"This":[130],"paper":[131],"proposes":[132],"PGCapping,":[133],"design":[136],"integrate":[138],"capping.":[146],"To":[147],"fully":[148],"utilize":[149],"headroom":[152],"reserved":[155],"through":[156],"gating,":[158],"PGCapping":[159,193],"enables":[160],"per-core":[161,171],"overclocking":[162,172],"turned-on":[164],"sequential":[168],"applications.":[169],"make":[174],"some":[175],"age":[177],"faster":[179],"than":[180,223],"others":[181],"thus":[183],"become":[184],"reliability":[186],"bottleneck":[187],"whole":[190],"system.":[191],"Therefore,":[192],"also":[194],"uses":[195],"balance":[199],"core":[201],"lifetimes.":[202],"Our":[203],"empirical":[204],"results":[205,247],"hardware":[208],"testbed":[209],"show":[210],"proposed":[213],"scheme":[214],"achieves":[215],"up":[216],"42.0%":[218],"average":[220],"application":[221],"five":[224],"state-of-the-art":[225],"capping":[227],"baselines":[228],"realistic":[230],"multi-core":[231],"applications,":[232],"i.e.,":[233],"mixed":[235],"group":[236],"PARSEC":[238],"SPEC":[240],"CPU2006":[241],"benchmarks.":[242],"Furthermore,":[243],"our":[244],"extensive":[245],"simulation":[246],"real-world":[249],"traces":[250],"demonstrate":[251],"lightweight":[254],"lifetime":[255,266],"balancing":[256],"algorithm":[257],"(based":[258],"gating)":[261],"increase":[263],"by":[267],"9.2%":[268],"average.":[270]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":10},{"year":2016,"cited_by_count":16},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}