{"id":"https://openalex.org/W2169665207","doi":"https://doi.org/10.1145/1854273.1854350","title":"A case for NUMA-aware contention management on multicore systems","display_name":"A case for NUMA-aware contention management on multicore systems","publication_year":2010,"publication_date":"2010-09-11","ids":{"openalex":"https://openalex.org/W2169665207","doi":"https://doi.org/10.1145/1854273.1854350","mag":"2169665207"},"language":"en","primary_location":{"id":"doi:10.1145/1854273.1854350","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1854273.1854350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038056852","display_name":"Sergey Blagodurov","orcid":"https://orcid.org/0009-0003-7412-5922"},"institutions":[{"id":"https://openalex.org/I18014758","display_name":"Simon Fraser University","ror":"https://ror.org/0213rcc28","country_code":"CA","type":"education","lineage":["https://openalex.org/I18014758"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Sergey Blagodurov","raw_affiliation_strings":["Simon Fraser University, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Simon Fraser University, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I18014758"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103162400","display_name":"Sergey Zhuravlev","orcid":null},"institutions":[{"id":"https://openalex.org/I18014758","display_name":"Simon Fraser University","ror":"https://ror.org/0213rcc28","country_code":"CA","type":"education","lineage":["https://openalex.org/I18014758"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Sergey Zhuravlev","raw_affiliation_strings":["Simon Fraser University, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Simon Fraser University, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I18014758"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021291662","display_name":"Alexandra Fedorova","orcid":"https://orcid.org/0000-0001-6805-7300"},"institutions":[{"id":"https://openalex.org/I18014758","display_name":"Simon Fraser University","ror":"https://ror.org/0213rcc28","country_code":"CA","type":"education","lineage":["https://openalex.org/I18014758"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Alexandra Fedorova","raw_affiliation_strings":["Simon Fraser University, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Simon Fraser University, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I18014758"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046649936","display_name":"Ali Kamali","orcid":"https://orcid.org/0000-0002-3913-1329"},"institutions":[{"id":"https://openalex.org/I18014758","display_name":"Simon Fraser University","ror":"https://ror.org/0213rcc28","country_code":"CA","type":"education","lineage":["https://openalex.org/I18014758"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Ali Kamali","raw_affiliation_strings":["Simon Fraser University, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Simon Fraser University, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I18014758"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5038056852"],"corresponding_institution_ids":["https://openalex.org/I18014758"],"apc_list":null,"apc_paid":null,"fwci":12.1191,"has_fulltext":false,"cited_by_count":213,"citation_normalized_percentile":{"value":0.98902938,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"557","last_page":"558"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8994801640510559},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5945064425468445},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5492938160896301},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5443886518478394},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.5414609313011169},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5407786965370178},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5383449792861938},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4983644485473633},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.48441579937934875},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.47083237767219543},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.44606202840805054},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.43210458755493164},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40361323952674866},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.35575437545776367},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23400726914405823},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.09910109639167786},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.09408852458000183}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8994801640510559},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5945064425468445},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5492938160896301},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5443886518478394},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5414609313011169},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5407786965370178},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5383449792861938},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4983644485473633},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.48441579937934875},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.47083237767219543},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.44606202840805054},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.43210458755493164},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40361323952674866},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.35575437545776367},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23400726914405823},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.09910109639167786},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.09408852458000183},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1854273.1854350","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1854273.1854350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities","score":0.7400000095367432}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W36050632","https://openalex.org/W48345810","https://openalex.org/W1964225254","https://openalex.org/W1985539519","https://openalex.org/W1994023216","https://openalex.org/W2005838647","https://openalex.org/W2017156338","https://openalex.org/W2059290792","https://openalex.org/W2064343267","https://openalex.org/W2066159952","https://openalex.org/W2071515131","https://openalex.org/W2083272082","https://openalex.org/W2098278566","https://openalex.org/W2100720297","https://openalex.org/W2129846162","https://openalex.org/W2134633067","https://openalex.org/W2151056818","https://openalex.org/W2154499141","https://openalex.org/W2168102371","https://openalex.org/W2170544909","https://openalex.org/W2171119362","https://openalex.org/W3112651258","https://openalex.org/W4240262711"],"related_works":["https://openalex.org/W4321458411","https://openalex.org/W254684032","https://openalex.org/W126098351","https://openalex.org/W2047684617","https://openalex.org/W3108993429","https://openalex.org/W2782503170","https://openalex.org/W2096506606","https://openalex.org/W4281924108","https://openalex.org/W2041174925","https://openalex.org/W2117533242"],"abstract_inverted_index":{"On":[0],"multicore":[1,82],"systems":[2],"contention":[3,33,103,137,166,224],"for":[4,138,181],"shared":[5],"resources":[6],"occurs":[7],"when":[8],"memory-intensive":[9],"threads":[10,44],"are":[11,85,207],"co-scheduled":[12],"on":[13,64,110,161],"cores":[14],"that":[15,68,89,102,146,227],"share":[16],"parts":[17],"of":[18,122,128,176,211],"the":[19,69,114,120,126,143,151,159,174,196,208,212],"memory":[20,27,47,75,79,93,98,139,203],"hierarchy,":[21],"such":[22],"as":[23,55,193,195],"last-level":[24],"caches":[25],"and":[26,96,167,220],"controllers.":[28,99],"Previous":[29],"work":[30,63,156],"investigated":[31],"how":[32],"could":[34],"be":[35],"addressed":[36],"via":[37],"scheduling.":[38],"A":[39],"contention-aware":[40,65,178,214],"scheduler":[41,115],"separates":[42],"competing":[43],"onto":[45],"separate":[46],"hierarchy":[48],"domains":[49],"to":[50,135,142],"eliminate":[51,136],"resource":[52,165],"sharing":[53],"and,":[54],"a":[56,106,177,188,222],"consequence,":[57],"mitigate":[58],"contention.":[59],"However,":[60],"all":[61],"previous":[62],"scheduling":[66,179,215],"assumed":[67],"underlying":[70],"system":[71],"is":[72,105,132,150,228],"UMA":[73],"(uniform":[74],"access":[76,94,148,169],"latencies,":[77],"single":[78],"controller).":[80],"Modern":[81],"systems,":[83,112],"however,":[84],"NUMA,":[86],"which":[87,206],"means":[88],"they":[90],"feature":[91],"non-uniform":[92],"latencies":[95],"multiple":[97],"We":[100,200],"discovered":[101],"management":[104,225],"lot":[107],"more":[108],"difficult":[109],"NUMA":[111,182,213],"because":[113],"must":[116],"not":[117],"only":[118],"consider":[119],"placement":[121,127],"threads,":[123],"but":[124],"also":[125,201],"their":[129],"memory.":[130],"This":[131,171,184],"mostly":[133],"required":[134],"controllers":[140],"contrary":[141],"popular":[144],"belief":[145],"remote":[147,168],"latency":[149],"dominant":[152],"concern.":[153],"In":[154],"this":[155],"we":[157,218],"quantify":[158],"effects":[160],"performance":[162],"imposed":[163],"by":[164],"latency.":[170],"analysis":[172],"inspires":[173],"design":[175],"algorithm":[180,185,190,226],"systems.":[183],"significantly":[186],"outperforms":[187],"NUMA-unaware":[189],"proposed":[191],"before":[192],"well":[194],"default":[197],"Linux":[198],"scheduler.":[199],"investigate":[202],"migration":[204],"strategies,":[205],"necessary":[209],"part":[210],"algorithm.":[216],"Finally,":[217],"propose":[219],"evaluate":[221],"new":[223],"priority-aware.":[229]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":11},{"year":2019,"cited_by_count":11},{"year":2018,"cited_by_count":14},{"year":2017,"cited_by_count":20},{"year":2016,"cited_by_count":21},{"year":2015,"cited_by_count":34},{"year":2014,"cited_by_count":22},{"year":2013,"cited_by_count":28},{"year":2012,"cited_by_count":17}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
