{"id":"https://openalex.org/W2010530256","doi":"https://doi.org/10.1145/17356.17380","title":"A functional level simulation engine of MAN-YO: a special purpose parallel machine for logic design automation","display_name":"A functional level simulation engine of MAN-YO: a special purpose parallel machine for logic design automation","publication_year":1986,"publication_date":"1986-05-01","ids":{"openalex":"https://openalex.org/W2010530256","doi":"https://doi.org/10.1145/17356.17380","mag":"2010530256"},"language":"en","primary_location":{"id":"doi:10.1145/17356.17380","is_oa":true,"landing_page_url":"https://doi.org/10.1145/17356.17380","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/17356.17380","source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/17356.17380","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088058883","display_name":"Toshiyuki Nakata","orcid":"https://orcid.org/0000-0001-6383-7105"},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Nakata","raw_affiliation_strings":["C&amp;C Systems Laboratories, NEC Corporation, 4-1-1Miyazaki Miyamae-ku Kawasaki 213, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"C&amp;C Systems Laboratories, NEC Corporation, 4-1-1Miyazaki Miyamae-ku Kawasaki 213, JAPAN","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090608277","display_name":"Nobuhiko Koike","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Koike","raw_affiliation_strings":["C&amp;C Systems Laboratories, NEC Corporation, 4-1-1Miyazaki Miyamae-ku Kawasaki 213, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"C&amp;C Systems Laboratories, NEC Corporation, 4-1-1Miyazaki Miyamae-ku Kawasaki 213, JAPAN","institution_ids":["https://openalex.org/I118347220"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14932743,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":"2","first_page":"202","last_page":"208"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7975179553031921},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.5880530476570129},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4714701473712921},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4712272882461548},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.44539666175842285},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.4137343764305115},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37472569942474365},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.366127073764801},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2644038200378418},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26207610964775085},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1348302960395813}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7975179553031921},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.5880530476570129},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4714701473712921},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4712272882461548},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.44539666175842285},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.4137343764305115},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37472569942474365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.366127073764801},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2644038200378418},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26207610964775085},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1348302960395813},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/17356.17380","is_oa":true,"landing_page_url":"https://doi.org/10.1145/17356.17380","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/17356.17380","source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.84.9731","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.84.9731","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://mprc.pku.cn/mentors/training/ISCAreading/1986/p202-nakata/p202-nakata.pdf","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/17356.17380","is_oa":true,"landing_page_url":"https://doi.org/10.1145/17356.17380","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/17356.17380","source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2010530256.pdf","grobid_xml":"https://content.openalex.org/works/W2010530256.grobid-xml"},"referenced_works_count":9,"referenced_works":["https://openalex.org/W69098491","https://openalex.org/W97614336","https://openalex.org/W1824389261","https://openalex.org/W2035476045","https://openalex.org/W2038615855","https://openalex.org/W2041074597","https://openalex.org/W2098525454","https://openalex.org/W2148752144","https://openalex.org/W2164357943"],"related_works":["https://openalex.org/W2045183646","https://openalex.org/W2162409446","https://openalex.org/W2109463584","https://openalex.org/W2504075107","https://openalex.org/W2354058185","https://openalex.org/W3214257365","https://openalex.org/W4312076519","https://openalex.org/W2161167665","https://openalex.org/W1984298705","https://openalex.org/W4247130854"],"abstract_inverted_index":{"The":[0,35,125],"architecture":[1,164],"of":[2,9,76,97,119,145,160,165],"a":[3,10,30,98,157],"proto-type":[4],"functional":[5,23,52,56,81,167],"level":[6,53,114,121,168],"simulator":[7,57,82,169],"element":[8,170],"massively":[11],"parallel":[12],"machine":[13],"(MAN-YO)":[14],"designed":[15],"for":[16,149],"logic":[17],"design":[18,180],"automation":[19],"is":[20,38,181],"presented.":[21],"At":[22],"level,":[24,109],"hardware":[25,31],"systems":[26],"are":[27,91],"described":[28],"in":[29,153],"description":[32,37,159],"language,":[33],"FDL.":[34],"FDL":[36,136],"compiled":[39,60],"into":[40,138],"stack":[41],"oriented":[42],"intermediate":[43],"language":[44],"instructions.":[45],"Communicating":[46],"with":[47],"other":[48],"gate":[49],"level/block":[50],"level/":[51],"processors,":[54],"each":[55],"interprets":[58],"the":[59,80,94,146,154,163,166,178],"instructions":[61],"and":[62,162],"simulates":[63],"various":[64],"circuits":[65],"using":[66],"4-value":[67,77],"logic.":[68],"In":[69],"order":[70],"to":[71],"realize":[72],"high":[73,116],"speed":[74,117],"processing":[75],"logic/arithmetic":[78],"operations,":[79],"utilizes":[83],"low-level":[84,105],"parallelism":[85,106],"realized":[86],"by":[87,93,132],"3":[88],"ALUs":[89],"which":[90],"controlled":[92],"different":[95],"fields":[96],"long":[99],"horizontal":[100],"type":[101],"microinstruction.":[102],"By":[103],"utilizing":[104],"at":[107],"processor":[108,113,155],"as":[110,112],"well":[111],"parallelism,":[115],"execution":[118],"mixed":[120],"simulation":[122],"becomes":[123],"possible.":[124],"system":[126],"also":[127,182],"provides":[128],"further":[129],"performance":[130,175],"enhancement":[131],"compiling":[133],"often":[134],"used":[135],"macros":[137],"microcode.":[139],"This":[140],"paper":[141],"describes":[142],"an":[143],"outline":[144],"MAN-YO":[147],"(Japanese":[148],"ten":[150],"thousand":[151],"leaf-nodes":[152],"tree),":[156],"brief":[158],"FDL,":[161],"(called":[171],"FDLPE).":[172],"A":[173],"rough":[174],"based":[176],"on":[177],"current":[179],"described.":[183]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
