{"id":"https://openalex.org/W2074465260","doi":"https://doi.org/10.1145/1731740.1731820","title":"FSM decomposition with application to FPGA synthesis","display_name":"FSM decomposition with application to FPGA synthesis","publication_year":2009,"publication_date":"2009-06-18","ids":{"openalex":"https://openalex.org/W2074465260","doi":"https://doi.org/10.1145/1731740.1731820","mag":"2074465260"},"language":"en","primary_location":{"id":"doi:10.1145/1731740.1731820","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1731740.1731820","pdf_url":null,"source":{"id":"https://openalex.org/S4210222260","display_name":"Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing","issn_l":"1313-8936","issn":["1313-8936","1313-9037"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069958724","display_name":"Alexander Sudnitson","orcid":null},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Alexander Sudnitson","raw_affiliation_strings":["","Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]},{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032307964","display_name":"Dmitri Mihhailov","orcid":"https://orcid.org/0000-0003-1167-2120"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Dmitri Mihhailov","raw_affiliation_strings":["","Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]},{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027798135","display_name":"Margus Kruus","orcid":"https://orcid.org/0000-0003-3515-1290"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Margus Kruus","raw_affiliation_strings":["","Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]},{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013217962","display_name":"Konstantin Tarletski","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Konstantin Tarletski","raw_affiliation_strings":[""],"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5069958724"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11218569,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8490827083587646},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.7233808040618896},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6939632892608643},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5755071640014648},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5651471018791199},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5329523682594299},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5228227376937866},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.49980974197387695},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4856066107749939},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.476977676153183},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.45701056718826294},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.41714510321617126},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3482738137245178},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.33234068751335144},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.22018766403198242},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13019326329231262},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06698170304298401}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8490827083587646},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.7233808040618896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6939632892608643},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5755071640014648},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5651471018791199},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5329523682594299},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5228227376937866},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.49980974197387695},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4856066107749939},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.476977676153183},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.45701056718826294},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.41714510321617126},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3482738137245178},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.33234068751335144},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.22018766403198242},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13019326329231262},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06698170304298401},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1731740.1731820","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1731740.1731820","pdf_url":null,"source":{"id":"https://openalex.org/S4210222260","display_name":"Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing","issn_l":"1313-8936","issn":["1313-8936","1313-9037"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323438","display_name":"Tallinna Tehnika\u00fclikool","ror":"https://ror.org/0443cwa12"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W151521611","https://openalex.org/W2059677035","https://openalex.org/W2101331965","https://openalex.org/W2122914389","https://openalex.org/W2149532166","https://openalex.org/W2149634175"],"related_works":["https://openalex.org/W2197466303","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W2139569078","https://openalex.org/W1512285683","https://openalex.org/W2187918628","https://openalex.org/W1748531671","https://openalex.org/W2367310356","https://openalex.org/W2136570321","https://openalex.org/W2359075490"],"abstract_inverted_index":{"This":[0],"paper":[1],"gives":[2],"an":[3],"overview":[4],"of":[5,31],"how":[6],"the":[7],"FSM":[8],"(finite":[9],"state":[10],"machine)":[11],"decomposition":[12],"techniques":[13],"coupled":[14],"with":[15],"FPGA":[16],"(field-programmable":[17],"gate":[18],"array)":[19],"technology":[20],"are":[21],"integrated":[22],"into":[23],"digital":[24],"design":[25],"educational":[26],"process":[27],"at":[28],"Tallinn":[29],"University":[30],"Technology":[32],"(TUT).":[33],"Paper":[34],"describes":[35],"software,":[36],"equipment":[37],"and":[38],"methodology":[39],"for":[40],"teaching":[41],"decomposition-based":[42],"logic":[43],"design.":[44]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
