{"id":"https://openalex.org/W2157890680","doi":"https://doi.org/10.1145/1117201.1117219","title":"Performance benefits of monolithically stacked 3D-FPGA","display_name":"Performance benefits of monolithically stacked 3D-FPGA","publication_year":2006,"publication_date":"2006-02-22","ids":{"openalex":"https://openalex.org/W2157890680","doi":"https://doi.org/10.1145/1117201.1117219","mag":"2157890680"},"language":"en","primary_location":{"id":"doi:10.1145/1117201.1117219","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060908808","display_name":"Mingjie Lin","orcid":"https://orcid.org/0000-0002-3225-4406"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mingjie Lin","raw_affiliation_strings":["Stanford University, CA"],"affiliations":[{"raw_affiliation_string":"Stanford University, CA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078716556","display_name":"Abbas El Gamal","orcid":"https://orcid.org/0000-0002-0853-0415"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abbas El Gamal","raw_affiliation_strings":["Stanford University, CA"],"affiliations":[{"raw_affiliation_string":"Stanford University, CA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040956103","display_name":"Yi-Chang Lu","orcid":"https://orcid.org/0000-0002-7638-0367"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yi-Chang Lu","raw_affiliation_strings":["Stanford University, CA"],"affiliations":[{"raw_affiliation_string":"Stanford University, CA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066440288","display_name":"S.S. Wong","orcid":"https://orcid.org/0000-0003-4361-1744"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Simon Wong","raw_affiliation_strings":["Stanford University, CA"],"affiliations":[{"raw_affiliation_string":"Stanford University, CA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5060908808"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":9.0263,"has_fulltext":false,"cited_by_count":96,"citation_normalized_percentile":{"value":0.9817378,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"113","last_page":"122"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7505613565444946},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6832013130187988},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6043304800987244},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.5625447630882263},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5619462132453918},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5000357627868652},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4977848529815674},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4771520495414734},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44008079171180725},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.41322070360183716},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.36819225549697876},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30955445766448975},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2716066539287567},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20114809274673462},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19907206296920776},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07550254464149475}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7505613565444946},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6832013130187988},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6043304800987244},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.5625447630882263},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5619462132453918},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5000357627868652},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4977848529815674},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4771520495414734},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44008079171180725},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.41322070360183716},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.36819225549697876},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30955445766448975},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2716066539287567},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20114809274673462},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19907206296920776},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07550254464149475},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1117201.1117219","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1117201.1117219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1494602065","https://openalex.org/W1523051745","https://openalex.org/W1589544645","https://openalex.org/W1830708738","https://openalex.org/W1893702321","https://openalex.org/W1903405547","https://openalex.org/W1980103179","https://openalex.org/W1980697206","https://openalex.org/W1984588379","https://openalex.org/W2013409221","https://openalex.org/W2045726766","https://openalex.org/W2097521167","https://openalex.org/W2099481418","https://openalex.org/W2106655287","https://openalex.org/W2113645429","https://openalex.org/W2116094656","https://openalex.org/W2119043051","https://openalex.org/W2120397377","https://openalex.org/W2133151023","https://openalex.org/W2133712953","https://openalex.org/W2138438526","https://openalex.org/W2138444824","https://openalex.org/W2139243942","https://openalex.org/W2139637699","https://openalex.org/W2141473386","https://openalex.org/W2146185334","https://openalex.org/W2150098004","https://openalex.org/W2162546785","https://openalex.org/W2170034300","https://openalex.org/W2170510975","https://openalex.org/W2536066754"],"related_works":["https://openalex.org/W3006681749","https://openalex.org/W2809889545","https://openalex.org/W1948588291","https://openalex.org/W3129152221","https://openalex.org/W2058461810","https://openalex.org/W2891188466","https://openalex.org/W1997318576","https://openalex.org/W2135286216","https://openalex.org/W2134239612","https://openalex.org/W2754644930"],"abstract_inverted_index":{"The":[0],"performance":[1],"benefits":[2],"of":[3,12,19,106],"a":[4,20,40,57,96,130],"monolithically":[5,131],"stacked":[6,16,132],"3D-FPGA,":[7],"whereby":[8],"the":[9,25,44,64,75,80,83,92,104,114,121,156,161],"programming":[10],"overhead":[11],"an":[13,107],"FPGA":[14],"is":[15,37,60,101,127],"on":[17],"top":[18,76],"standard":[21],"CMOS":[22,122],"layer":[23,123],"containing":[24],"logic":[26,48,85,139],"blocks":[27],"and":[28,51,67,78,87,110,147],"interconnects,":[29],"are":[30,124],"investigated.":[31],"A":[32],"Virtex-II":[33],"style":[34],"2D-FPGA":[35,158],"fabric":[36],"used":[38],"as":[39,91,117],"baseline":[41,93,157],"for":[42],"quantifying":[43],"relative":[45],"improvements":[46],"in":[47,120,160],"density,":[49,140],"delay,":[50,146],"power":[52,153],"consumption":[53,154],"achieved":[54],"by":[55],"such":[56],"3D-FPGA.":[58],"It":[59],"assumed":[61],"that":[62,79,100,129],"only":[63],"pass-transistor":[65,111],"switches":[66,112],"configuration":[68,97],"memory":[69,98],"cells":[70],"can":[71,134],"be":[72],"moved":[73],"to":[74],"layers":[77],"3D-FPGA":[81,133],"employs":[82],"same":[84,115,162],"block":[86],"programmable":[88],"interconnect":[89],"architecture":[90],"2D-FPGA.":[94],"Assuming":[95],"cell":[99,109],"\u2264":[102],"0.7":[103],"area":[105],"SRAM":[108],"having":[113],"characteristics":[116],"nMOS":[118],"devices":[119],"used,":[125],"it":[126],"shown":[128],"achieve":[135],"3.2":[136],"times":[137,142,149],"higher":[138],"1.7":[141,148],"lower":[143,150],"critical":[144],"path":[145],"total":[151],"dynamic":[152],"than":[155],"fabricated":[159],"65nm":[163],"technology":[164],"node.":[165]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":16},{"year":2012,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}