{"id":"https://openalex.org/W2168518353","doi":"https://doi.org/10.1145/1016568.1016573","title":"Verification and test challenges in SoC designs","display_name":"Verification and test challenges in SoC designs","publication_year":2004,"publication_date":"2004-09-04","ids":{"openalex":"https://openalex.org/W2168518353","doi":"https://doi.org/10.1145/1016568.1016573","mag":"2168518353"},"language":"en","primary_location":{"id":"doi:10.1145/1016568.1016573","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016573","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111989757","display_name":"C\u00e9sar Augusto Due\u00f1as M.","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"C\u00e9sar Augusto Due\u00f1as M.","raw_affiliation_strings":["Freescale Semiconductor Inc., Jaguari\u00fana, Brazil"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc., Jaguari\u00fana, Brazil","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5111989757"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5266,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.68419679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7461431622505188},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6431999206542969},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.6339043974876404},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6260703802108765},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6143214702606201},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4938376545906067},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4356013834476471},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.43326571583747864},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4297647178173065},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4260683059692383},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42133766412734985},{"id":"https://openalex.org/keywords/presentation","display_name":"Presentation (obstetrics)","score":0.42082738876342773},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.4087616205215454},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16113710403442383},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15927451848983765}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7461431622505188},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6431999206542969},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.6339043974876404},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6260703802108765},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6143214702606201},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4938376545906067},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4356013834476471},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.43326571583747864},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4297647178173065},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4260683059692383},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42133766412734985},{"id":"https://openalex.org/C2777601897","wikidata":"https://www.wikidata.org/wiki/Q3409113","display_name":"Presentation (obstetrics)","level":2,"score":0.42082738876342773},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4087616205215454},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16113710403442383},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15927451848983765},{"id":"https://openalex.org/C126838900","wikidata":"https://www.wikidata.org/wiki/Q77604","display_name":"Radiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1016568.1016573","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1016568.1016573","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th symposium on Integrated circuits and system design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5899999737739563,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2106507440","https://openalex.org/W3209085687","https://openalex.org/W4375946032","https://openalex.org/W4389429005","https://openalex.org/W2116002481","https://openalex.org/W2536819812","https://openalex.org/W1585773602"],"abstract_inverted_index":{"SoC":[0],"(System-on-Chip)":[1],"designs":[2],"have":[3],"introduced":[4],"several":[5,25,88],"new":[6,61],"challenges":[7],"for":[8],"the":[9,16,58,69,81,117],"functional":[10,18,70],"verification":[11,71,105],"and":[12,28,43,72,95,103,106,115,126],"test":[13,107],"disciplines.":[14],"Besides":[15],"ever-growing":[17],"complexity,":[19],"we":[20],"need":[21],"to":[22,31,77,122],"manage":[23],"from":[24],"clock":[26],"domains":[27],"low-power":[29],"modes":[30],"all":[32],"sorts":[33],"of":[34,46,51,60,93],"IP":[35,54],"blocks":[36],"like":[37],"processors,":[38],"complex":[39],"peripherals,":[40],"analog":[41],"functions":[42],"different":[44,91],"kinds":[45],"embedded":[47],"memories.":[48],"The":[49],"reuse":[50],"3rd":[52],"party":[53],"may":[55,74,84],"help":[56,68],"accelerating":[57],"design":[59],"products,":[62],"but":[63],"it":[64,73],"usually":[65],"does":[66],"not":[67],"even":[75],"add":[76],"its":[78],"complexity.":[79],"Also,":[80],"same":[82],"die":[83],"be":[85],"used":[86],"in":[87],"packages":[89],"with":[90,124],"number":[92],"pins":[94],"bond-out":[96],"options.":[97],"This":[98],"presentation":[99],"will":[100],"discuss":[101],"these":[102],"other":[104],"challenges.":[108],"It":[109],"also":[110],"describes":[111],"what":[112],"tools,":[113],"techniques":[114],"methodologies":[116],"industry":[118],"is":[119],"currently":[120],"using":[121],"cope":[123],"them,":[125],"finalizes":[127],"outlining":[128],"some":[129],"future":[130],"directions.":[131]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}