{"id":"https://openalex.org/W7147699585","doi":"https://doi.org/10.1145/3803551","title":"Mitigating the Bandwidth Wall via Data-Streaming System\u2013Accelerator Co-Design","display_name":"Mitigating the Bandwidth Wall via Data-Streaming System\u2013Accelerator Co-Design","publication_year":2026,"publication_date":"2026-04-01","ids":{"openalex":"https://openalex.org/W7147699585","doi":"https://doi.org/10.1145/3803551"},"language":"en","primary_location":{"id":"doi:10.1145/3803551","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3803551","pdf_url":null,"source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://doi.org/10.1145/3803551","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113182978","display_name":"Qunyou Liu","orcid":"https://orcid.org/0000-0002-7410-502X"},"institutions":[{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Qunyou Liu","raw_affiliation_strings":["Embedded Systems Laboratory, \u00c9cole polytechnique f\u00e9d\u00e9rale de Lausanne Facult\u00e9 des sciences et techniques de l'Ing\u00e9nieur"],"raw_orcid":"https://orcid.org/0000-0002-7410-502X","affiliations":[{"raw_affiliation_string":"Embedded Systems Laboratory, \u00c9cole polytechnique f\u00e9d\u00e9rale de Lausanne Facult\u00e9 des sciences et techniques de l'Ing\u00e9nieur","institution_ids":["https://openalex.org/I4210145666","https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050801793","display_name":"Marina Zapater","orcid":"https://orcid.org/0000-0002-6971-1965"},"institutions":[{"id":"https://openalex.org/I173439891","display_name":"HES-SO University of Applied Sciences and Arts Western Switzerland","ror":"https://ror.org/01xkakk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I173439891"]},{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Marina Zapater","raw_affiliation_strings":["Embedded Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne Facult\u00e9 des Sciences et Techniques de l'Ing\u00e9nieur","School of Engineering and Management Vaud (HEIG-VD), University of Applied Sciences Western Switzerland (HES-SO)"],"raw_orcid":"https://orcid.org/0000-0002-6971-1965","affiliations":[{"raw_affiliation_string":"Embedded Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne Facult\u00e9 des Sciences et Techniques de l'Ing\u00e9nieur","institution_ids":["https://openalex.org/I4210145666","https://openalex.org/I5124864"]},{"raw_affiliation_string":"School of Engineering and Management Vaud (HEIG-VD), University of Applied Sciences Western Switzerland (HES-SO)","institution_ids":["https://openalex.org/I173439891"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000910924","display_name":"D. Atienza","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"David Atienza","raw_affiliation_strings":["Embedded Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne Facult\u00e9 des Sciences et Techniques de l'Ing\u00e9nieur"],"raw_orcid":"https://orcid.org/0000-0001-9536-4947","affiliations":[{"raw_affiliation_string":"Embedded Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne Facult\u00e9 des Sciences et Techniques de l'Ing\u00e9nieur","institution_ids":["https://openalex.org/I4210145666","https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.43039612,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"23","issue":"2","first_page":"1","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7675999999046326,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7675999999046326,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.07129999995231628,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.0340999998152256,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.6700999736785889},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.48170000314712524},{"id":"https://openalex.org/keywords/transformer","display_name":"Transformer","score":0.46779999136924744},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4675999879837036},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.44119998812675476},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.3797999918460846},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.3619000017642975},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.3601999878883362},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.35899999737739563}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8894000053405762},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.6700999736785889},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.48170000314712524},{"id":"https://openalex.org/C66322947","wikidata":"https://www.wikidata.org/wiki/Q11658","display_name":"Transformer","level":3,"score":0.46779999136924744},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4675999879837036},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4611000120639801},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4514999985694885},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.44119998812675476},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.3797999918460846},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37860000133514404},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.3619000017642975},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.3601999878883362},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.35899999737739563},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.3521000146865845},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.3476000130176544},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.3472000062465668},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3109999895095825},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.29109999537467957},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.28619998693466187},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.2833000123500824},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.2808000147342682},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.2705000042915344},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.26919999718666077},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26109999418258667},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.2590999901294708},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.25839999318122864},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2563999891281128},{"id":"https://openalex.org/C19527686","wikidata":"https://www.wikidata.org/wiki/Q1665453","display_name":"System integration","level":2,"score":0.25279998779296875},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.2502000033855438}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3803551","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3803551","pdf_url":null,"source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3803551","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3803551","pdf_url":null,"source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2147657366","https://openalex.org/W2158116338","https://openalex.org/W2606722458","https://openalex.org/W2904348962","https://openalex.org/W2963341956","https://openalex.org/W3094271339","https://openalex.org/W3102175148","https://openalex.org/W3102510044","https://openalex.org/W3106090013","https://openalex.org/W3138287635","https://openalex.org/W3161571687","https://openalex.org/W3203530736","https://openalex.org/W3213528054","https://openalex.org/W4221013715","https://openalex.org/W4249553981","https://openalex.org/W4324266631","https://openalex.org/W4393139774","https://openalex.org/W4394975824","https://openalex.org/W7130724054"],"related_works":[],"abstract_inverted_index":{"Transformers":[0],"have":[1],"revolutionized":[2],"AI":[3],"in":[4,186,224],"natural":[5],"language":[6],"processing":[7],"and":[8,15,35,64,72,77,113,121,159,168,180,209,215,231,239,265],"computer":[9],"vision,":[10],"but":[11],"their":[12],"enormous":[13],"computation":[14],"memory":[16,161,250],"demands":[17],"pose":[18],"significant":[19],"challenges":[20],"for":[21,279],"hardware":[22,61,81],"acceleration.":[23],"In":[24],"practice,":[25],"end-to-end":[26],"throughput":[27],"is":[28,100],"often":[29],"limited":[30],"by":[31,56],"paged":[32,263],"data":[33,213],"movement":[34],"interconnect":[36,126],"bandwidth,":[37,127],"not":[38,269],"just":[39],"raw":[40],"MAC":[41],"count.":[42],"This":[43],"work":[44],"proposes":[45],"a":[46,59,87,94,107,115,228,246],"unified":[47],"system\u2013accelerator":[48],"co-design":[49],"approach":[50,200],"to":[51,123,188,221],"efficiently":[52],"accelerate":[53],"transformer":[54,206,281],"inference":[55,226,282],"jointly":[57],"optimizing":[58],"novel":[60,178],"matrix":[62,96],"accelerator":[63,92],"its":[65],"system":[66,139,151,216,285],"integration":[67],"with":[68,172,201],"paged,":[69],"streaming":[70,131,264],"dataflows":[71],"explicit":[73],"overlap":[74,267],"of":[75,118,147,155,234,255,258],"compute":[76],"transfer.":[78],"On":[79,137],"the":[80,138,148,181,256,275],"side,":[82,140],"we":[83,141,243],"introduce":[84],"MatrixFlow":[85],",":[86,144,268],"loosely\u2010coupled":[88],"16\u00d7":[89],"16":[90],"systolic\u2010array":[91],"featuring":[93],"block\u2010based":[95],"multiplication":[97],"method":[98],"that":[99,245],"page-aligned":[101],"(4":[102],"KB":[103],"tiles),":[104],"uses":[105],"only":[106],"small":[108],"(\u224820":[109],"KB)":[110],"on-chip":[111,135],"buffer,":[112],"runs":[114],"pipelined":[116],"schedule":[117],"DMA,":[119],"compute,":[120],"DMA-out":[122],"fully":[124],"utilize":[125],"emphasizing":[128],"standard":[129,156,247],"DMA-driven":[130],"rather":[132],"than":[133],"large":[134,270],"reuse.":[136],"develop":[142],"Gem5\u2010AcceSys":[143,182],"an":[145],"extension":[146],"gem5":[149,202],"full":[150],"simulator":[152],"allowing":[153],"exploration":[154],"interconnects":[157],"(PCIe)":[158],"configurable":[160],"hierarchies":[162],"including":[163],"Direct-Memory":[164],"(DM),":[165],"Direct-Cache":[166],"(DC),":[167],"Device-Memory":[169],"(DevMem)":[170],"modes":[171],"SMMU/TLB":[173],"effects.":[174],"Through":[175],"co\u2010design,":[176],"MatrixFlow\u2019s":[177],"dataflow":[179],"platform":[183],"are":[184],"tuned":[185],"tandem":[187],"alleviate":[189],"data\u2010movement":[190],"bottlenecks":[191],"without":[192],"requiring":[193],"specialized":[194],"CPU\u2010instruction\u2010set":[195],"modifications.":[196],"We":[197],"validate":[198],"our":[199],"simulations":[203],"on":[204],"representative":[205],"models":[207],"(BERT":[208],"ViT)":[210],"across":[211],"multiple":[212],"types":[214],"setups.":[217],"Results":[218],"demonstrate":[219],"up":[220],"22\u00d7":[222],"speed\u2010up":[223],"end\u2010to\u2010end":[225],"over":[227,236],"CPU\u2010only":[229],"baseline":[230],"performance":[232,257],"gains":[233],"5\u00d7\u20138\u00d7":[235],"state\u2010of\u2010the\u2010art":[237],"loosely\u2010":[238],"tightly\u2010coupled":[240],"accelerators.":[241],"Furthermore,":[242],"show":[244],"PCIe-based":[248],"host":[249],"design":[251],"can":[252],"achieve":[253],"\u223c80%":[254],"on\u2010device":[259],"HBM":[260],"memory.":[261],"Overall,":[262],"pipeline":[266],"local":[271],"SRAMs,":[272],"emerge":[273],"as":[274],"most":[276],"effective":[277],"knobs":[278],"efficient":[280],"under":[283],"realistic":[284],"constraints.":[286]},"counts_by_year":[],"updated_date":"2026-06-26T06:17:10.115597","created_date":"2026-04-02T00:00:00"}
