{"id":"https://openalex.org/W7166329177","doi":"https://doi.org/10.1145/3801487.3801810","title":"Implications of Supporting Compressed Instructions in Area-Optimized Bit-Serial RISC-V Cores","display_name":"Implications of Supporting Compressed Instructions in Area-Optimized Bit-Serial RISC-V Cores","publication_year":2026,"publication_date":"2026-05-19","ids":{"openalex":"https://openalex.org/W7166329177","doi":"https://doi.org/10.1145/3801487.3801810"},"language":null,"primary_location":{"id":"doi:10.1145/3801487.3801810","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3801487.3801810","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3801487.3801810","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092092559","display_name":"Meinhard Kissich","orcid":"https://orcid.org/0000-0003-4810-8312"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Meinhard Kissich","raw_affiliation_strings":["Graz University of Technology, Graz, Austria"],"raw_orcid":"https://orcid.org/0000-0003-4810-8312","affiliations":[{"raw_affiliation_string":"Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5139504870","display_name":"Daniel Traussnig","orcid":"https://orcid.org/0009-0007-2121-5691"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Daniel Traussnig","raw_affiliation_strings":["Graz University of Technology, Graz, Austria"],"raw_orcid":"https://orcid.org/0009-0007-2121-5691","affiliations":[{"raw_affiliation_string":"Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072094059","display_name":"Marcel Baunach","orcid":"https://orcid.org/0000-0002-3716-2682"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Marcel Baunach","raw_affiliation_strings":["Graz University of Technology, Graz, Austria"],"raw_orcid":"https://orcid.org/0000-0002-3716-2682","affiliations":[{"raw_affiliation_string":"Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4092182"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.95543951,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"39","last_page":"48"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.30709999799728394,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.30709999799728394,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.18449999392032623,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.14990000426769257,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6572999954223633},{"id":"https://openalex.org/keywords/memory-footprint","display_name":"Memory footprint","score":0.5997999906539917},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5827000141143799},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5813999772071838},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.49000000953674316},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.45190000534057617},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.4399000108242035},{"id":"https://openalex.org/keywords/cover","display_name":"Cover (algebra)","score":0.4253999888896942},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.4221999943256378},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.4104999899864197}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7741000056266785},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6572999954223633},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6129000186920166},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.5997999906539917},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5827000141143799},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5813999772071838},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.49000000953674316},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.460099995136261},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.45190000534057617},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.4399000108242035},{"id":"https://openalex.org/C2780428219","wikidata":"https://www.wikidata.org/wiki/Q16952335","display_name":"Cover (algebra)","level":2,"score":0.4253999888896942},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.4221999943256378},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.4104999899864197},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4034000039100647},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.3465999960899353},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.3377000093460083},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3149999976158142},{"id":"https://openalex.org/C42058472","wikidata":"https://www.wikidata.org/wiki/Q810214","display_name":"Base (topology)","level":2,"score":0.3147999942302704},{"id":"https://openalex.org/C59656382","wikidata":"https://www.wikidata.org/wiki/Q191536","display_name":"Conjunction (astronomy)","level":2,"score":0.31439998745918274},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.31439998745918274},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.30889999866485596},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.29019999504089355},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.28870001435279846},{"id":"https://openalex.org/C138236772","wikidata":"https://www.wikidata.org/wiki/Q25098575","display_name":"Edge device","level":3,"score":0.27900001406669617},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.2775000035762787},{"id":"https://openalex.org/C2982832238","wikidata":"https://www.wikidata.org/wiki/Q5531640","display_name":"General purpose","level":2,"score":0.27469998598098755},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.27379998564720154},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.2705000042915344},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.2687999904155731},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2615000009536743},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.257099986076355},{"id":"https://openalex.org/C124851039","wikidata":"https://www.wikidata.org/wiki/Q2665459","display_name":"Compressed sensing","level":2,"score":0.25060001015663147},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.2502000033855438},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.25}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3801487.3801810","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3801487.3801810","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3801487.3801810","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3801487.3801810","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.47042831778526306,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2128767249","https://openalex.org/W2292759015","https://openalex.org/W2766918834","https://openalex.org/W2945816340","https://openalex.org/W2946485102","https://openalex.org/W2951749218","https://openalex.org/W2963255460","https://openalex.org/W3216373256","https://openalex.org/W4296437373","https://openalex.org/W4400224459","https://openalex.org/W4400275989","https://openalex.org/W4402827382","https://openalex.org/W4413755252","https://openalex.org/W4415285685"],"related_works":[],"abstract_inverted_index":{"Bit-serial":[0],"RISC-V":[1,53],"cores":[2],"cover":[3],"a":[4,164],"distinctive":[5],"corner":[6],"in":[7,20,80,89,151,163,189],"the":[8,21,50,57,62,72,81,84,101,124,144,156,171,192,195,200],"design":[9],"space,":[10],"making":[11],"them":[12],"particularly":[13],"interesting":[14],"for":[15,100,136,177],"highly":[16],"area-constrained,":[17],"ultra-low-cost":[18],"applications":[19],"IoT":[22],"and":[23,105,119,128,199],"extreme":[24],"edge":[25],"computing,":[26],"such":[27],"as":[28,132,134],"smart":[29],"sensors":[30],"or":[31],"single-use":[32],"healthcare":[33],"devices.":[34],"Given":[35],"their":[36,111],"stringent":[37],"focus":[38],"on":[39,78,123,184],"area":[40],"demand,":[41],"each":[42],"feature":[43],"must":[44],"be":[45,187],"carefully":[46],"considered.":[47],"One":[48],"is":[49,87,175],"use":[51],"of":[52,91,110,147,170],"compressed":[54,69,149],"instructions":[55,70,150],"by":[56,76,159],"RVC":[58,85,98,173],"extension":[59,86],"to":[60,161,186],"reduce":[61,71],"memory":[63],"footprint":[64],"and,":[65],"consequently,":[66],"costs.":[67],"While":[68],"required":[73],"ROM":[74],"size":[75,158],"22.4%":[77],"average":[79],"Embench":[82],"suite,":[83],"costly":[88],"terms":[90],"hardware":[92,145],"resources.":[93],"This":[94],"work":[95],"proposes":[96],"three":[97],"implementations":[99,174],"bit-serial":[102,152],"FazyRV":[103,166],"core":[104],"provides":[106],"an":[107,137],"in-depth":[108],"analysis":[109],"implications.":[112],"We":[113],"utilize":[114],"open-source":[115],"tools":[116],"wherever":[117],"applicable":[118],"base":[120],"our":[121],"evaluations":[122],"iCE40,":[125],"ECP5,":[126],"GateMate,":[127],"7-Series":[129],"FPGA":[130],"architectures,":[131],"well":[133],"estimates":[135],"IHP-SG13G2":[138],"ASIC":[139],"implementation.":[140],"Our":[141],"findings":[142],"highlight":[143],"cost":[146],"supporting":[148],"cores,":[153],"which":[154],"increases":[155],"implementation":[157],"14.5%":[160],"58%":[162],"1-bit":[165],"variant.":[167],"Ultimately,":[168],"none":[169],"proposed":[172],"optimal":[176],"all":[178],"targets.":[179],"Thus,":[180],"we":[181],"provide":[182],"guidance":[183],"decisions":[185],"made":[188],"conjunction":[190],"with":[191],"target":[193],"architecture,":[194],"intended":[196],"system":[197],"performance,":[198],"firmware.":[201]},"counts_by_year":[],"updated_date":"2026-06-28T06:20:29.262167","created_date":"2026-06-28T00:00:00"}
