{"id":"https://openalex.org/W7165179387","doi":"https://doi.org/10.1145/3787109.3816376","title":"Agentic Hardware Synthesis with CDM Supergatesfor Efficient Design Generation","display_name":"Agentic Hardware Synthesis with CDM Supergatesfor Efficient Design Generation","publication_year":2026,"publication_date":"2026-06-18","ids":{"openalex":"https://openalex.org/W7165179387","doi":"https://doi.org/10.1145/3787109.3816376"},"language":null,"primary_location":{"id":"doi:10.1145/3787109.3816376","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3816376","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3787109.3816376","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5138906280","display_name":"Srija Vuppala","orcid":"https://orcid.org/0009-0001-4718-5300"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]},{"id":"https://openalex.org/I87573096","display_name":"University of North Texas at Dallas","ror":"https://ror.org/01n51v443","country_code":"US","type":"education","lineage":["https://openalex.org/I87573096"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srija Vuppala","raw_affiliation_strings":["ECE Dept., University of Texas at Dallas, Dallas, TX, USA"],"raw_orcid":"https://orcid.org/0009-0001-4718-5300","affiliations":[{"raw_affiliation_string":"ECE Dept., University of Texas at Dallas, Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319","https://openalex.org/I87573096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098980261","display_name":"Yogeswar Reddy Thota","orcid":"https://orcid.org/0009-0002-0192-1066"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]},{"id":"https://openalex.org/I87573096","display_name":"University of North Texas at Dallas","ror":"https://ror.org/01n51v443","country_code":"US","type":"education","lineage":["https://openalex.org/I87573096"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yogeswar Reddy Thota","raw_affiliation_strings":["ECE Dept., University of Texas at Dallas, Dallas, TX, USA"],"raw_orcid":"https://orcid.org/0009-0002-0192-1066","affiliations":[{"raw_affiliation_string":"ECE Dept., University of Texas at Dallas, Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319","https://openalex.org/I87573096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138910530","display_name":"Mahathi Ellanti","orcid":"https://orcid.org/0009-0002-2616-7370"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]},{"id":"https://openalex.org/I87573096","display_name":"University of North Texas at Dallas","ror":"https://ror.org/01n51v443","country_code":"US","type":"education","lineage":["https://openalex.org/I87573096"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mahathi Ellanti","raw_affiliation_strings":["ECE Dept., University of Texas at Dallas, Dallas, TX, USA"],"raw_orcid":"https://orcid.org/0009-0002-2616-7370","affiliations":[{"raw_affiliation_string":"ECE Dept., University of Texas at Dallas, Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319","https://openalex.org/I87573096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138842944","display_name":"Harshith Navin Lachappa","orcid":"https://orcid.org/0009-0007-6461-3956"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]},{"id":"https://openalex.org/I87573096","display_name":"University of North Texas at Dallas","ror":"https://ror.org/01n51v443","country_code":"US","type":"education","lineage":["https://openalex.org/I87573096"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Harshith Navin Lachappa","raw_affiliation_strings":["ECE Dept., University of Texas at Dallas, Dallas, TX, USA"],"raw_orcid":"https://orcid.org/0009-0007-6461-3956","affiliations":[{"raw_affiliation_string":"ECE Dept., University of Texas at Dallas, Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319","https://openalex.org/I87573096"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060036961","display_name":"Avesta Sasan","orcid":"https://orcid.org/0000-0002-4052-8075"},"institutions":[{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Avesta Sasan","raw_affiliation_strings":["ECE Dept., University of California, Davis, Davis, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-4052-8075","affiliations":[{"raw_affiliation_string":"ECE Dept., University of California, Davis, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051431139","display_name":"Tooraj Nikoubin","orcid":"https://orcid.org/0000-0003-1724-3503"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]},{"id":"https://openalex.org/I87573096","display_name":"University of North Texas at Dallas","ror":"https://ror.org/01n51v443","country_code":"US","type":"education","lineage":["https://openalex.org/I87573096"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tooraj Nikoubin","raw_affiliation_strings":["ECE Dept., University of Texas at Dallas, Dallas, TX, USA"],"raw_orcid":"https://orcid.org/0000-0003-1724-3503","affiliations":[{"raw_affiliation_string":"ECE Dept., University of Texas at Dallas, Dallas, TX, USA","institution_ids":["https://openalex.org/I162577319","https://openalex.org/I87573096"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.71828442,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"194","last_page":"199"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5324000120162964,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5324000120162964,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.30149999260902405,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.03139999881386757,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8418999910354614},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5914000272750854},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4934999942779541},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.3837999999523163},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.36910000443458557},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.3686999976634979},{"id":"https://openalex.org/keywords/oracle","display_name":"Oracle","score":0.35989999771118164},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.3488999903202057},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.3431999981403351},{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.3382999897003174}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8418999910354614},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6496999859809875},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5914000272750854},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4934999942779541},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4553999900817871},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.390500009059906},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.3837999999523163},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3750999867916107},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.36910000443458557},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.3686999976634979},{"id":"https://openalex.org/C55166926","wikidata":"https://www.wikidata.org/wiki/Q2892946","display_name":"Oracle","level":2,"score":0.35989999771118164},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.3488999903202057},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.3431999981403351},{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.3382999897003174},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3357999920845032},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.3357999920845032},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.322299987077713},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.32190001010894775},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.30709999799728394},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.3050999939441681},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3050000071525574},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.3005000054836273},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.29980000853538513},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2955000102519989},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.2921000123023987},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.2838999927043915},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.27900001406669617},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.26510000228881836},{"id":"https://openalex.org/C164226766","wikidata":"https://www.wikidata.org/wiki/Q7293202","display_name":"Rank (graph theory)","level":2,"score":0.2628999948501587},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.258899986743927},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.25839999318122864},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.25429999828338623}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3787109.3816376","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3816376","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3787109.3816376","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3816376","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2912607283","https://openalex.org/W2951537853","https://openalex.org/W4391681217","https://openalex.org/W4392972103","https://openalex.org/W4393145478","https://openalex.org/W4393145520","https://openalex.org/W4402194443","https://openalex.org/W4403511190","https://openalex.org/W4409282449","https://openalex.org/W4414420252"],"related_works":[],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2],"end-to-end":[3],"hardware":[4,20],"agent":[5,150],"that":[6],"translates":[7],"multimodal":[8],"specifications":[9],"including":[10,140],"free-form":[11],"text,":[12],"PDF,":[13],"DOCX,":[14],"audio,":[15],"and":[16,38,78,105,127,147,163],"video":[17],"into":[18,75],"verified":[19,35],"across":[21,49],"four":[22],"levels":[23],"of":[24,69],"abstraction:":[25],"behavioral":[26,92],"RTL,":[27],"gate-level":[28],"netlist":[29],"with":[30,41],"GLS,":[31],"transistor-level":[32,82],"CMOS":[33],"SPICE":[34],"by":[36,137],"ngspice,":[37],"layout-preview":[39],"SVG":[40],"ITRS-based":[42],"physical":[43,159],"estimates":[44],"(area,":[45],"power,":[46],"latency,":[47],"energy)":[48],"configurable":[50],"technology":[51],"nodes":[52],"(130":[53],"nm\u20135":[54],"nm).":[55],"A":[56,98,115],"novel":[57],"Cell":[58],"Design":[59],"Methodology":[60],"(CDM)":[61],"supergate":[62],"knowledge-injection":[63],"mechanism":[64],"embeds":[65],"a":[66,119,128],"structured":[67,99],"manifest":[68],"multi-output,":[70],"multi-functional":[71],"CDM":[72],"cell":[73],"patterns":[74],"the":[76,124],"generation":[77],"repair":[79],"stages,":[80],"grounding":[81],"synthesis":[83],"in":[84],"provably":[85],"correct":[86],"pmos/nmos":[87],"topologies":[88],"rather":[89],"than":[90],"unconstrained":[91],"inference.":[93],"When":[94],"processing":[95],"multi-source":[96],"inputs.":[97],"intermediate":[100],"representation":[101],"canonicalizes":[102],"all":[103],"inputs,":[104],"Gemini":[106],"Embeddings":[107],"rank":[108],"evidence":[109],"chunks":[110],"for":[111,167],"retrieval-augmented":[112],"specification":[113],"extraction.":[114],"two-oracle":[116],"strategy":[117],"uses":[118],"deterministic":[120],"spec-derived":[121],"testbench":[122,130],"as":[123,131],"primary":[125],"oracle":[126],"smoke":[129],"fallback.":[132],"Verification":[133],"is":[134],"performed":[135],"entirely":[136],"external":[138],"tools,":[139],"Verilator,":[141],"Icarus":[142],"Verilog,":[143],"Yosys,":[144],"SymbiYosys,":[145],"OpenSTA,":[146],"ngspice.":[148],"The":[149],"reports":[151],"RTL":[152],"complexity":[153],"metrics,":[154],"transistor":[155],"counts,":[156],"layout":[157],"dimensions,":[158],"estimates,":[160],"formal":[161],"assertions,":[162],"per-iteration":[164],"audit":[165],"data":[166],"reproducibility.":[168]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-06-19T00:00:00"}