{"id":"https://openalex.org/W7165119193","doi":"https://doi.org/10.1145/3787109.3815253","title":"An Agile Design Framework for Resource-Efficient and Parameterizable Edge ISPs","display_name":"An Agile Design Framework for Resource-Efficient and Parameterizable Edge ISPs","publication_year":2026,"publication_date":"2026-06-18","ids":{"openalex":"https://openalex.org/W7165119193","doi":"https://doi.org/10.1145/3787109.3815253"},"language":null,"primary_location":{"id":"doi:10.1145/3787109.3815253","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3815253","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3787109.3815253","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5138895267","display_name":"Xitong Jiang","orcid":"https://orcid.org/0009-0004-3126-8779"},"institutions":[{"id":"https://openalex.org/I198091727","display_name":"Tiangong University","ror":"https://ror.org/00xsr9m91","country_code":"CN","type":"education","lineage":["https://openalex.org/I198091727"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xitong Jiang","raw_affiliation_strings":["Tiangong University, Tianjin, China"],"raw_orcid":"https://orcid.org/0009-0004-3126-8779","affiliations":[{"raw_affiliation_string":"Tiangong University, Tianjin, China","institution_ids":["https://openalex.org/I198091727"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020075105","display_name":"Qingzeng Song","orcid":"https://orcid.org/0000-0002-5406-294X"},"institutions":[{"id":"https://openalex.org/I198091727","display_name":"Tiangong University","ror":"https://ror.org/00xsr9m91","country_code":"CN","type":"education","lineage":["https://openalex.org/I198091727"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qingzeng Song","raw_affiliation_strings":["Tiangong University, Tianjin, China"],"raw_orcid":"https://orcid.org/0000-0002-5406-294X","affiliations":[{"raw_affiliation_string":"Tiangong University, Tianjin, China","institution_ids":["https://openalex.org/I198091727"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041134676","display_name":"Yongjiang Xue","orcid":"https://orcid.org/0000-0002-3487-0309"},"institutions":[{"id":"https://openalex.org/I198091727","display_name":"Tiangong University","ror":"https://ror.org/00xsr9m91","country_code":"CN","type":"education","lineage":["https://openalex.org/I198091727"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongjiang Xue","raw_affiliation_strings":["Tiangong University, Tianjin, China"],"raw_orcid":"https://orcid.org/0000-0002-3487-0309","affiliations":[{"raw_affiliation_string":"Tiangong University, Tianjin, China","institution_ids":["https://openalex.org/I198091727"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5138935759","display_name":"Weigang Kong","orcid":"https://orcid.org/0009-0003-2638-1550"},"institutions":[{"id":"https://openalex.org/I198091727","display_name":"Tiangong University","ror":"https://ror.org/00xsr9m91","country_code":"CN","type":"education","lineage":["https://openalex.org/I198091727"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weigang Kong","raw_affiliation_strings":["Tiangong University, Tianjin, China"],"raw_orcid":"https://orcid.org/0009-0003-2638-1550","affiliations":[{"raw_affiliation_string":"Tiangong University, Tianjin, China","institution_ids":["https://openalex.org/I198091727"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063901096","display_name":"Fei Qiao","orcid":"https://orcid.org/0000-0002-5054-9590"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fei Qiao","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-5054-9590","affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5138333977","display_name":"Mingze Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I198091727","display_name":"Tiangong University","ror":"https://ror.org/00xsr9m91","country_code":"CN","type":"education","lineage":["https://openalex.org/I198091727"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingze Sun","raw_affiliation_strings":["Tiangong University, Tianjin, China"],"raw_orcid":"https://orcid.org/0009-0003-4539-7638","affiliations":[{"raw_affiliation_string":"Tiangong University, Tianjin, China","institution_ids":["https://openalex.org/I198091727"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.93811768,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"890","last_page":"897"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.6509000062942505,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.6509000062942505,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.08179999887943268,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.04560000076889992,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6717000007629395},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4758000075817108},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.4747999906539917},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.43959999084472656},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.40959998965263367},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.39329999685287476},{"id":"https://openalex.org/keywords/handshaking","display_name":"Handshaking","score":0.38519999384880066},{"id":"https://openalex.org/keywords/agile-software-development","display_name":"Agile software development","score":0.37950000166893005},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.3625999987125397},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.3601999878883362}],"concepts":[{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6717000007629395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6211000084877014},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5533000230789185},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4758000075817108},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.4747999906539917},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.43959999084472656},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4336000084877014},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.40959998965263367},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.39329999685287476},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3921999931335449},{"id":"https://openalex.org/C58861099","wikidata":"https://www.wikidata.org/wiki/Q548838","display_name":"Handshaking","level":2,"score":0.38519999384880066},{"id":"https://openalex.org/C14185376","wikidata":"https://www.wikidata.org/wiki/Q30232","display_name":"Agile software development","level":2,"score":0.37950000166893005},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3625999987125397},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.3601999878883362},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.3549000024795532},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3515999913215637},{"id":"https://openalex.org/C2778751112","wikidata":"https://www.wikidata.org/wiki/Q835016","display_name":"Window (computing)","level":2,"score":0.3458000123500824},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.33970001339912415},{"id":"https://openalex.org/C137981799","wikidata":"https://www.wikidata.org/wiki/Q1369184","display_name":"Reusability","level":3,"score":0.3393999934196472},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.33309999108314514},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.3285999894142151},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3192000091075897},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.3149000108242035},{"id":"https://openalex.org/C3913047","wikidata":"https://www.wikidata.org/wiki/Q1956265","display_name":"sync","level":3,"score":0.3127000033855438},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.3125},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.3066999912261963},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.29829999804496765},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.28619998693466187},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.2720000147819519},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26330000162124634},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.260699987411499},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.2565999925136566},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.25360000133514404},{"id":"https://openalex.org/C185177783","wikidata":"https://www.wikidata.org/wiki/Q3332814","display_name":"Megabit","level":2,"score":0.2515000104904175}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3787109.3815253","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3815253","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3787109.3815253","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3815253","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1980208272","https://openalex.org/W1983394510","https://openalex.org/W2466242877","https://openalex.org/W2615178951","https://openalex.org/W2788102204","https://openalex.org/W3086751423","https://openalex.org/W4240172596","https://openalex.org/W4310251122","https://openalex.org/W4310454550","https://openalex.org/W4380874681","https://openalex.org/W4407041151","https://openalex.org/W4410628609"],"related_works":[],"abstract_inverted_index":{"Facing":[0],"the":[1,23,48,61,90,97,130],"real-time":[2,101],"and":[3,57,104,107,112,137,159],"resource":[4,124],"constraints":[5],"of":[6,26,140],"edge":[7],"imaging":[8],"systems,":[9],"this":[10],"paper":[11],"presents":[12],"a":[13,33,45,66,76,117,170],"highly":[14],"parameterizable":[15],"ISP":[16],"hardware":[17],"pipeline":[18,49,99],"in":[19],"SpinalHDL.":[20],"To":[21],"overcome":[22],"poor":[24],"reusability":[25],"manually":[27],"maintained":[28],"Verilog":[29,121],"designs,":[30],"we":[31,64],"adopt":[32],"configuration-driven":[34],"generation":[35],"paradigm":[36],"to":[37,82,116,129],"construct":[38],"an":[39],"end-to-end":[40],"RAW-to-YUV":[41],"streaming":[42],"architecture.":[43],"Under":[44],"unified":[46,134],"ISPConfig,":[47],"supports":[50],"flexible":[51],"module":[52],"chaining,":[53],"compile-time":[54],"structural":[55],"specialization,":[56],"timing-consistent":[58],"integration.":[59],"At":[60],"microarchitectural":[62],"level,":[63],"introduce":[65],"generic":[67],"Window":[68,132],"Generator":[69],"that":[70,96],"combines":[71],"parameterized":[72],"line":[73],"buffers":[74],"with":[75,150],"deterministic":[77],"Skid":[78],"Buffer-based":[79],"flow-control":[80],"shell":[81],"preserve":[83],"pixel-level":[84],"synchronization":[85],"under":[86],"backpressure.":[87],"Experiments":[88],"on":[89,175],"AMD":[91],"Xilinx":[92],"Kria":[93],"KV260":[94],"show":[95],"generated":[98,145],"sustains":[100],"1080p60":[102],"processing":[103],"reduces":[105],"LUT":[106],"DSP":[108],"utilization":[109],"by":[110],"19.0%":[111],"28.8%,":[113],"respectively,":[114],"relative":[115],"functionally":[118],"matched":[119],"hand-coded":[120],"baseline.":[122],"The":[123,144],"gains":[125],"are":[126],"mainly":[127],"attributed":[128],"shared":[131],"Generator,":[133],"inter-stage":[135],"interfaces,":[136],"generator-time":[138],"elimination":[139],"duplicated":[141],"glue":[142],"logic.":[143],"design":[146],"also":[147],"agrees":[148],"well":[149],"software":[151],"references,":[152],"achieving":[153],"39.71":[154],"dB":[155],"PSNR,":[156],"0.9636":[157],"SSIM,":[158],"1.255":[160],"MAE,":[161],"while":[162],"representative":[163,178],"requirement":[164],"changes":[165],"can":[166],"be":[167],"completed":[168],"within":[169],"20-minute":[171],"RTL-to-simulation":[172],"regression":[173],"loop":[174],"average":[176],"across":[177],"modification":[179],"tasks.":[180]},"counts_by_year":[],"updated_date":"2026-06-19T15:51:49.773706","created_date":"2026-06-19T00:00:00"}