{"id":"https://openalex.org/W7165174937","doi":"https://doi.org/10.1145/3787109.3815240","title":"CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation","display_name":"CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation","publication_year":2026,"publication_date":"2026-06-18","ids":{"openalex":"https://openalex.org/W7165174937","doi":"https://doi.org/10.1145/3787109.3815240"},"language":null,"primary_location":{"id":"doi:10.1145/3787109.3815240","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3815240","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3787109.3815240","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025724355","display_name":"Sohan Salahuddin Mugdho","orcid":null},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sohan Salahuddin Mugdho","raw_affiliation_strings":["Iowa State university of Science and Technology, Ames, IA, USA"],"raw_orcid":"https://orcid.org/0009-0004-2670-285X","affiliations":[{"raw_affiliation_string":"Iowa State university of Science and Technology, Ames, IA, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103107089","display_name":"Md. Shahedul Hasan","orcid":"https://orcid.org/0000-0002-7182-0677"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Md. Shahedul Hasan","raw_affiliation_strings":["Iowa State university of Science and Technology, Ames, IA, USA"],"raw_orcid":"https://orcid.org/0000-0002-7182-0677","affiliations":[{"raw_affiliation_string":"Iowa State university of Science and Technology, Ames, IA, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046050149","display_name":"Brahmdutta Dixit","orcid":"https://orcid.org/0009-0008-4471-3877"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]},{"id":"https://openalex.org/I4210101327","display_name":"Twin Cities Orthopedics","ror":"https://ror.org/01en4s460","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210101327"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brahmdutta Dixit","raw_affiliation_strings":["University of Minnesota Twin Cities, Minneapolis, USA"],"raw_orcid":"https://orcid.org/0009-0008-4471-3877","affiliations":[{"raw_affiliation_string":"University of Minnesota Twin Cities, Minneapolis, USA","institution_ids":["https://openalex.org/I4210101327","https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038396376","display_name":"Yang Lv","orcid":"https://orcid.org/0000-0001-9062-309X"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]},{"id":"https://openalex.org/I4210101327","display_name":"Twin Cities Orthopedics","ror":"https://ror.org/01en4s460","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210101327"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yang Lv","raw_affiliation_strings":["University of Minnesota Twin Cities, Minneapolis, USA"],"raw_orcid":"https://orcid.org/0000-0001-9062-309X","affiliations":[{"raw_affiliation_string":"University of Minnesota Twin Cities, Minneapolis, USA","institution_ids":["https://openalex.org/I4210101327","https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062474441","display_name":"Jian\u2010Ping Wang","orcid":"https://orcid.org/0000-0003-2815-6624"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]},{"id":"https://openalex.org/I4210101327","display_name":"Twin Cities Orthopedics","ror":"https://ror.org/01en4s460","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210101327"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jian-Ping Wang","raw_affiliation_strings":["University of Minnesota Twin Cities, Minneapolis, MN, USA"],"raw_orcid":"https://orcid.org/0000-0003-2815-6624","affiliations":[{"raw_affiliation_string":"University of Minnesota Twin Cities, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I4210101327","https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039113028","display_name":"Cheng Wang","orcid":"https://orcid.org/0000-0002-8815-2871"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng Wang","raw_affiliation_strings":["Iowa State university of Science and Technology, Ames, IA, USA"],"raw_orcid":"https://orcid.org/0000-0002-8815-2871","affiliations":[{"raw_affiliation_string":"Iowa State university of Science and Technology, Ames, IA, USA","institution_ids":["https://openalex.org/I173911158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"557","last_page":"563"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.326200008392334,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.326200008392334,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.16300000250339508,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.13809999823570251,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7166000008583069},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6782000064849854},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.5838000178337097},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.5024999976158142},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.4733999967575073},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4575999975204468},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.42250001430511475},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4077000021934509},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.39559999108314514},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.36970001459121704}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8061000108718872},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7166000008583069},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6782000064849854},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.5838000178337097},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.5024999976158142},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48399999737739563},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.4733999967575073},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.46790000796318054},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4575999975204468},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.42250001430511475},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41119998693466187},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4077000021934509},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.39559999108314514},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3709000051021576},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.36970001459121704},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.3684999942779541},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.35589998960494995},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.34860000014305115},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.3325999975204468},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.3312000036239624},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.32899999618530273},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.3262999951839447},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.3208000063896179},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.3091999888420105},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.30230000615119934},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.29980000853538513},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.29910001158714294},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2973000109195709},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2971000075340271},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.28619998693466187},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.2851000130176544},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.28439998626708984},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.2838999927043915},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.27390000224113464},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.27250000834465027},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.271699994802475},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.2703000009059906},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.26339998841285706},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.2615000009536743},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.25760000944137573}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3787109.3815240","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3815240","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3787109.3815240","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3787109.3815240","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Great Lakes Symposium on VLSI 2026","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.902458667755127,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1999151859","https://openalex.org/W2010202670","https://openalex.org/W2057386187","https://openalex.org/W2112796928","https://openalex.org/W2194775991","https://openalex.org/W2474451066","https://openalex.org/W2518281301","https://openalex.org/W2523535373","https://openalex.org/W2613989746","https://openalex.org/W2756167909","https://openalex.org/W2761132374","https://openalex.org/W2765234579","https://openalex.org/W2766489088","https://openalex.org/W2801000640","https://openalex.org/W2884227506","https://openalex.org/W2919115771","https://openalex.org/W2942415134","https://openalex.org/W2945829174","https://openalex.org/W2974067241","https://openalex.org/W3092378515","https://openalex.org/W3102223484","https://openalex.org/W3133253223","https://openalex.org/W3134526034","https://openalex.org/W3187014530","https://openalex.org/W4292121737","https://openalex.org/W4313254474","https://openalex.org/W4386365329","https://openalex.org/W4387789930","https://openalex.org/W4400985292","https://openalex.org/W4401212105","https://openalex.org/W4401568841","https://openalex.org/W4404471204","https://openalex.org/W4408468172","https://openalex.org/W4410086824","https://openalex.org/W4410582955","https://openalex.org/W7129048108","https://openalex.org/W7129098652"],"related_works":[],"abstract_inverted_index":{"Deep":[0],"neural":[1],"networks":[2],"(DNNs)":[3],"have":[4],"achieved":[5],"state-of-the-art":[6],"performance":[7],"across":[8],"diverse":[9],"domains.":[10],"However,":[11,52],"typical":[12],"Von":[13],"Neumann":[14],"compute":[15],"paradigms":[16],"face":[17],"severe":[18],"memory":[19],"bottlenecks.":[20],"Emerging":[21],"near-memory":[22],"and":[23,63,125,135,173],"compute-in-memory":[24],"approaches":[25],"alleviate":[26],"this":[27],"but":[28],"incur":[29],"significant":[30],"peripheral":[31,45],"overhead.":[32],"Computational":[33],"Random":[34],"Access":[35],"Memory":[36],"(CRAM)":[37],"based":[38],"on":[39,149],"MRAM":[40,54,76],"enables":[41],"in-situ":[42],"logic":[43],"without":[44],"overhead,":[46],"offering":[47],"a":[48,105],"dense,":[49],"energy-efficient":[50],"solution.":[51],"probabilistic":[53],"switching":[55],"induces":[56],"gate-level":[57],"errors":[58],"that":[59],"limit":[60],"the":[61,71,114,145],"scalability":[62],"reliability":[64],"of":[65,74,116,144,164],"CRAM":[66,80,90,157],"for":[67,93,139],"accelerating":[68],"DNN.":[69],"Moreover,":[70],"large":[72],"number":[73],"sequential":[75],"writes":[77],"severely":[78],"constrains":[79],"throughput.":[81],"To":[82],"address":[83],"these":[84],"challenges,":[85],"we":[86],"propose":[87],"an":[88,131],"error-resilient":[89],"(CRAM-ER)":[91],"architecture":[92,111,148],"scalable":[94],"in-memory":[95],"matrix-vector":[96],"multiplications":[97],"(MVMs).":[98],"Our":[99],"error-aware":[100,132],"hardware-software":[101],"co-design":[102],"framework":[103],"leverages":[104],"hybrid":[106,147],"spintronic-CRAM":[107],"+":[108],"CMOS":[109],"adder-tree":[110],"to":[112,161],"mitigate":[113],"impact":[115],"device-level":[117],"errors,":[118],"demonstrating":[119],"MVM":[120],"functionality":[121],"with":[122],"high":[123],"area":[124],"energy":[126,171],"efficiency.":[127],"We":[128],"further":[129],"develop":[130],"model":[133],"fine-tuning":[134],"fine-grained":[136],"error":[137,141],"correction":[138],"enhanced":[140],"resilience.":[142],"Evaluations":[143],"CMOS+spintronic":[146],"DNN":[150],"benchmarks":[151],"show":[152],"near-lossless":[153],"accuracy":[154],"while":[155],"reducing":[156],"latency":[158],"by":[159],"up":[160],"2":[162],"orders":[163],"magnitude,":[165],"outperforming":[166],"CPU/GPU+high-bandwidth":[167],"DRAM":[168],"in":[169],"both":[170],"efficiency":[172],"energy-delay":[174],"product.":[175]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-06-19T00:00:00"}