{"id":"https://openalex.org/W7134901369","doi":"https://doi.org/10.1145/3779212.3790201","title":"Performance Predictability in Heterogeneous Memory","display_name":"Performance Predictability in Heterogeneous Memory","publication_year":2026,"publication_date":"2026-03-10","ids":{"openalex":"https://openalex.org/W7134901369","doi":"https://doi.org/10.1145/3779212.3790201"},"language":null,"primary_location":{"id":"doi:10.1145/3779212.3790201","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3779212.3790201","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3779212.3790201","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103173952","display_name":"Jinshu Liu","orcid":"https://orcid.org/0000-0002-2490-5176"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jinshu Liu","raw_affiliation_strings":["Virginia Tech, Blacksburg, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-2490-5176","affiliations":[{"raw_affiliation_string":"Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128799651","display_name":"Hanchen Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hanchen Xu","raw_affiliation_strings":["Virginia Tech, Blacksburg, VA, USA"],"raw_orcid":"https://orcid.org/0009-0004-8578-7099","affiliations":[{"raw_affiliation_string":"Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063512602","display_name":"Daniel S. Berger","orcid":"https://orcid.org/0000-0002-3911-1512"},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel S. Berger","raw_affiliation_strings":["Microsoft and University of Washington, Redmond, USA"],"raw_orcid":"https://orcid.org/0000-0002-3911-1512","affiliations":[{"raw_affiliation_string":"Microsoft and University of Washington, Redmond, USA","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019483717","display_name":"Marcos K. Aguilera","orcid":"https://orcid.org/0000-0003-3489-2468"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marcos K. Aguilera","raw_affiliation_strings":["NVIDIA, Santa Clara, USA"],"raw_orcid":"https://orcid.org/0000-0003-3489-2468","affiliations":[{"raw_affiliation_string":"NVIDIA, Santa Clara, USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002675628","display_name":"Huaicheng Li","orcid":"https://orcid.org/0000-0002-3155-0203"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Huaicheng Li","raw_affiliation_strings":["Virginia Tech, Blacksburg, USA"],"raw_orcid":"https://orcid.org/0000-0002-3155-0203","affiliations":[{"raw_affiliation_string":"Virginia Tech, Blacksburg, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15891648,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1413","last_page":"1429"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.973800003528595,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.973800003528595,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.007300000172108412,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.006599999964237213,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.8407999873161316},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7195000052452087},{"id":"https://openalex.org/keywords/predictability","display_name":"Predictability","score":0.6898000240325928},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.6567999720573425},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.5292999744415283},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5170999765396118},{"id":"https://openalex.org/keywords/slowdown","display_name":"Slowdown","score":0.41609999537467957},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4090999960899353}],"concepts":[{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.8407999873161316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8111000061035156},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7195000052452087},{"id":"https://openalex.org/C197640229","wikidata":"https://www.wikidata.org/wiki/Q2534066","display_name":"Predictability","level":2,"score":0.6898000240325928},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.6567999720573425},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.5292999744415283},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5170999765396118},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4259999990463257},{"id":"https://openalex.org/C2777242750","wikidata":"https://www.wikidata.org/wiki/Q31351","display_name":"Slowdown","level":2,"score":0.41609999537467957},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4090999960899353},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3725000023841858},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.36329999566078186},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.30230000615119934},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.3018999993801117},{"id":"https://openalex.org/C147297375","wikidata":"https://www.wikidata.org/wiki/Q6674930","display_name":"Look-ahead","level":2,"score":0.30079999566078186},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.2955000102519989},{"id":"https://openalex.org/C2777115002","wikidata":"https://www.wikidata.org/wiki/Q7168246","display_name":"Performance prediction","level":2,"score":0.29179999232292175},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.27959999442100525},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.2646999955177307}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3779212.3790201","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3779212.3790201","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3779212.3790201","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3779212.3790201","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2036895660","https://openalex.org/W4318541517","https://openalex.org/W4318767786","https://openalex.org/W4327930415","https://openalex.org/W4327930439","https://openalex.org/W4408901606","https://openalex.org/W4411091774"],"related_works":[],"abstract_inverted_index":{"Heterogeneous":[0],"memory":[1],"combining":[2],"DRAM":[3,33],"and":[4,76,99,124,134,139],"CXL":[5,37,49,101],"exhibits":[6],"variable":[7],"performance,":[8],"yet":[9],"existing":[10,137],"metrics":[11],"correlate":[12],"weakly":[13],"with":[14],"actual":[15],"slowdown.":[16,26],"We":[17,112],"present":[18],"CAMP,":[19],"a":[20,32,36,81],"principled":[21],"framework":[22],"for":[23,39,84],"predicting":[24],"CXL-induced":[25],"Our":[27],"key":[28],"insight":[29],"is":[30],"that":[31,88,114],"run":[34,38],"(plus":[35],"bandwidth-bound":[40],"workloads)":[41],"exposes":[42],"the":[43],"causal":[44],"microarchitectural":[45],"pressure":[46],"points":[47],"where":[48],"latency":[50],"translates":[51],"into":[52,69],"additional":[53],"processor":[54],"stall":[55],"cycles.":[56],"CAMP":[57,78,103],"captures":[58],"these":[59,115],"signals":[60],"using":[61],"12":[62],"performance":[63,90,129],"counters":[64],"to":[65,132],"analytically":[66],"decompose":[67],"slowdown":[68],"three":[70,100],"orthogonal":[71],"components:":[72],"demand":[73],"reads,":[74],"cache/prefetching,":[75],"stores.":[77],"also":[79],"introduces":[80],"closed-form":[82],"model":[83],"software-based":[85],"weighted":[86],"interleaving":[87,123],"predicts":[89],"across":[91],"DRAM--CXL":[92],"ratios.":[93],"Across":[94],"265":[95],"workloads":[96],"on":[97],"NUMA":[98],"devices,":[102],"achieves":[104],"91--97%":[105],"prediction":[106],"accuracy":[107],"within":[108],"10%":[109],"absolute":[110],"error.":[111],"demonstrate":[113],"models":[116],"enable":[117],"practical":[118],"system":[119],"policies,":[120],"including":[121],"''Best-shot''":[122],"colocated":[125],"workload":[126],"placement,":[127],"improving":[128],"by":[130],"up":[131],"21%":[133],"23%":[135],"over":[136],"tiering":[138],"colocation":[140],"approaches.":[141]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-03-12T00:00:00"}