{"id":"https://openalex.org/W7134910744","doi":"https://doi.org/10.1145/3779212.3790141","title":"Co-Exploration of RISC-V Processor Microarchitectures and FreeRTOS Extensions for Lower Context-Switch Latency","display_name":"Co-Exploration of RISC-V Processor Microarchitectures and FreeRTOS Extensions for Lower Context-Switch Latency","publication_year":2026,"publication_date":"2026-03-10","ids":{"openalex":"https://openalex.org/W7134910744","doi":"https://doi.org/10.1145/3779212.3790141"},"language":null,"primary_location":{"id":"doi:10.1145/3779212.3790141","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3779212.3790141","pdf_url":null,"source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3779212.3790141","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5119790751","display_name":"Markus Scheck","orcid":"https://orcid.org/0009-0006-3098-3177"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Scheck","raw_affiliation_strings":["Technical University of Darmstadt, Darmstadt, Hesse, Germany"],"raw_orcid":"https://orcid.org/0009-0006-3098-3177","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Darmstadt, Hesse, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5095880846","display_name":"Tammo M\u00fcrmann","orcid":"https://orcid.org/0009-0004-6617-5230"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Tammo M\u00fcrmann","raw_affiliation_strings":["Technical University of Darmstadt, Darmstadt, Hesse, Germany"],"raw_orcid":"https://orcid.org/0009-0004-6617-5230","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Darmstadt, Hesse, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125745915","display_name":"A. Koch","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andreas Koch","raw_affiliation_strings":["Technical University of Darmstadt, Darmstadt, Hesse, Germany"],"raw_orcid":"https://orcid.org/0000-0002-1164-3082","affiliations":[{"raw_affiliation_string":"Technical University of Darmstadt, Darmstadt, Hesse, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"394","last_page":"408"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9293000102043152,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9293000102043152,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.03370000049471855,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.0071000000461936,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7900000214576721},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7657999992370605},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5787000060081482},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5695000290870667},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.47440001368522644},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.40880000591278076},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.37700000405311584},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.3361000120639801}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7900000214576721},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7657999992370605},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7314000129699707},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.691100001335144},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5787000060081482},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5695000290870667},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.47440001368522644},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.40880000591278076},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.37700000405311584},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.3361000120639801},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.32260000705718994},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.30329999327659607},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.29260000586509705},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2903999984264374},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.26910001039505005},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.26820001006126404},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.26759999990463257},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.26179999113082886},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2612999975681305},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.26019999384880066},{"id":"https://openalex.org/C35939892","wikidata":"https://www.wikidata.org/wiki/Q1139923","display_name":"Embedded operating system","level":3,"score":0.2581000030040741},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.25780001282691956},{"id":"https://openalex.org/C28472234","wikidata":"https://www.wikidata.org/wiki/Q213666","display_name":"Real-time operating system","level":2,"score":0.2572999894618988},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.25540000200271606},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.25540000200271606}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3779212.3790141","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3779212.3790141","pdf_url":null,"source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3779212.3790141","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3779212.3790141","pdf_url":null,"source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1974591841","https://openalex.org/W1995705225","https://openalex.org/W2017937196","https://openalex.org/W2064639033","https://openalex.org/W2103820545","https://openalex.org/W2105296397","https://openalex.org/W2127000736","https://openalex.org/W2129261226","https://openalex.org/W2154716491","https://openalex.org/W2168226456","https://openalex.org/W2936567838","https://openalex.org/W2963255460","https://openalex.org/W4288081317","https://openalex.org/W4393059230","https://openalex.org/W4414603096"],"related_works":[],"abstract_inverted_index":{"Embedded":[0],"real-time":[1,83,177],"systems":[2],"must":[3],"respond":[4],"to":[5,12,75,109,118,129,150],"external":[6],"events":[7],"within":[8],"tightly":[9],"bounded":[10],"timeframes":[11],"ensure":[13],"safety,":[14],"correctness,":[15],"and":[16,45,60,79,112,125,159,170],"reliability.":[17],"While":[18],"Real-Time":[19],"Operating":[20],"Systems":[21],"(RTOSes)":[22],"ease":[23],"the":[24,39,87,180],"development":[25],"of":[26,41,93,103],"complex":[27],"applications":[28],"by":[29],"providing":[30],"abstractions":[31],"for":[32,56,163,175,182],"multi-tasked":[33],"execution,":[34],"they":[35],"introduce":[36],"overheads":[37,137],"in":[38,81,121,138],"form":[40],"task":[42],"switching":[43],"latency":[44,78,124],"jitter,":[46],"which":[47],"impact":[48],"timing":[49,64],"predictability.":[50],"Minimizing":[51],"these":[52],"effects":[53],"is":[54],"essential":[55],"reducing":[57],"response":[58],"times":[59],"enabling":[61],"robust":[62],"worst-case":[63],"analysis.":[65],"We":[66],"present":[67],"RTOSUnit,":[68],"a":[69,101,168],"configurable":[70],"hardware":[71],"acceleration":[72,108],"unit":[73],"designed":[74],"reduce":[76],"context-switch":[77,111,123],"jitter":[80,132],"embedded":[82,164,187],"systems.":[84,165],"By":[85],"integrating":[86],"RTOSUnit":[88,115,166],"into":[89,185],"three":[90],"RISC-V":[91],"cores":[92],"varying":[94],"complexity,":[95],"we":[96],"demonstrate":[97],"its":[98],"portability.":[99],"Through":[100],"range":[102,142],"configurations,":[104],"from":[105,143],"lightweight":[106],"scheduling":[107],"full":[110],"-preloading":[113],"support,":[114],"achieves":[116],"up":[117],"76%":[119],"reduction":[120],"mean":[122],"can":[126],"be":[127],"configured":[128],"completely":[130],"eliminate":[131],"on":[133],"selected":[134],"cores.":[135],"Area":[136],"22nm":[139],"ASIC":[140],"implementations":[141],"negligible":[144],"(within":[145],"EDA":[146],"tool":[147],"heuristics":[148],"noise)":[149],"44\\,%,":[151],"with":[152],"all":[153],"configurations":[154],"maintaining":[155],"viable":[156],"operating":[157],"frequencies":[158],"power":[160],"envelopes":[161],"suitable":[162],"offers":[167],"flexible":[169],"efficient,":[171],"open-source.":[172],"https://github.com/esa-tu-darmstadt/RTOSUnit_Integration":[173],"foundation":[174],"hardware-assisted":[176],"scheduling,":[178],"paving":[179],"way":[181],"broader":[183],"integration":[184],"future":[186],"SoCs.":[188]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-17T09:13:05.818461","created_date":"2026-03-12T00:00:00"}
