{"id":"https://openalex.org/W4415104332","doi":"https://doi.org/10.1145/3771845","title":"InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems","display_name":"InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems","publication_year":2025,"publication_date":"2025-10-13","ids":{"openalex":"https://openalex.org/W4415104332","doi":"https://doi.org/10.1145/3771845"},"language":"en","primary_location":{"id":"doi:10.1145/3771845","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3771845","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1145/3771845","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066464351","display_name":"Arnab Raha","orcid":"https://orcid.org/0000-0002-8848-1069"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Arnab Raha","raw_affiliation_strings":["Intel Corporation","Intel Corporation, Santa Clara, United States"],"raw_orcid":"https://orcid.org/0000-0002-8848-1069","affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, United States","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043655176","display_name":"Sandeep Krishna Thirumala","orcid":"https://orcid.org/0000-0001-9448-324X"},"institutions":[{"id":"https://openalex.org/I11912373","display_name":"Micron (United States)","ror":"https://ror.org/02fv52296","country_code":"US","type":"company","lineage":["https://openalex.org/I11912373"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandeep Krishna Thirumala","raw_affiliation_strings":["Micron Technology Inc","Micron Technology Inc, Boise, United States"],"raw_orcid":"https://orcid.org/0000-0001-9448-324X","affiliations":[{"raw_affiliation_string":"Micron Technology Inc","institution_ids":["https://openalex.org/I11912373"]},{"raw_affiliation_string":"Micron Technology Inc, Boise, United States","institution_ids":["https://openalex.org/I11912373"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044276472","display_name":"Sumeet Kumar Gupta","orcid":"https://orcid.org/0000-0001-5609-9722"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sumeet Kumar Gupta","raw_affiliation_strings":["Purdue University","Purdue University, West Lafayette, United States"],"raw_orcid":"https://orcid.org/0000-0001-5609-9722","affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University, West Lafayette, United States","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102009759","display_name":"Vijay Raghunathan","orcid":"https://orcid.org/0000-0003-4713-5386"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijay Raghunathan","raw_affiliation_strings":["Purdue University","Purdue University, West Lafayette, United States"],"raw_orcid":"https://orcid.org/0000-0003-4713-5386","affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University, West Lafayette, United States","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23770621,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"31","issue":"1","first_page":"1","last_page":"44"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.6132000088691711},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5266000032424927},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.517799973487854},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4984999895095825},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.47530001401901245},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4325999915599823},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.40459999442100525},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.38190001249313354},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.38029998540878296}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8640999794006348},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.6132000088691711},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5266000032424927},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.517799973487854},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4984999895095825},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.47530001401901245},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.462799996137619},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4325999915599823},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4163999855518341},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.40459999442100525},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.38190001249313354},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.38029998540878296},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.37119999527931213},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3693999946117401},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.36559998989105225},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.36410000920295715},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.3458999991416931},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3330000042915344},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.3221000134944916},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3208000063896179},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.3068999946117401},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.29600000381469727},{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.29100000858306885},{"id":"https://openalex.org/C41661131","wikidata":"https://www.wikidata.org/wiki/Q220764","display_name":"Interrupt","level":3,"score":0.27480000257492065},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2720000147819519},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2615000009536743},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.2524999976158142},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.25040000677108765}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3771845","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3771845","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3771845","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3771845","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":68,"referenced_works":["https://openalex.org/W1131252562","https://openalex.org/W2024335183","https://openalex.org/W2034151099","https://openalex.org/W2051108935","https://openalex.org/W2112796928","https://openalex.org/W2133724338","https://openalex.org/W2300242332","https://openalex.org/W2516459979","https://openalex.org/W2562308138","https://openalex.org/W2588666075","https://openalex.org/W2609357516","https://openalex.org/W2612839290","https://openalex.org/W2734358244","https://openalex.org/W2744369623","https://openalex.org/W2772111147","https://openalex.org/W2787453651","https://openalex.org/W2798554798","https://openalex.org/W2798654995","https://openalex.org/W2799043997","https://openalex.org/W2889527112","https://openalex.org/W2899868573","https://openalex.org/W2900227741","https://openalex.org/W2916854910","https://openalex.org/W2946086434","https://openalex.org/W2952429406","https://openalex.org/W2963122961","https://openalex.org/W2963446207","https://openalex.org/W2978448132","https://openalex.org/W2989523235","https://openalex.org/W3000301330","https://openalex.org/W3013080934","https://openalex.org/W3017282344","https://openalex.org/W3021304221","https://openalex.org/W3037354233","https://openalex.org/W3046549256","https://openalex.org/W3046920646","https://openalex.org/W3083149649","https://openalex.org/W3088772051","https://openalex.org/W3091175932","https://openalex.org/W3115938264","https://openalex.org/W3176381399","https://openalex.org/W3194966730","https://openalex.org/W3200382295","https://openalex.org/W3217124456","https://openalex.org/W4200346503","https://openalex.org/W4200393040","https://openalex.org/W4206710119","https://openalex.org/W4210278476","https://openalex.org/W4212816501","https://openalex.org/W4225755231","https://openalex.org/W4226400219","https://openalex.org/W4251871580","https://openalex.org/W4283708377","https://openalex.org/W4283817132","https://openalex.org/W4285331444","https://openalex.org/W4308477818","https://openalex.org/W4311453553","https://openalex.org/W4313478540","https://openalex.org/W4317927906","https://openalex.org/W4362473790","https://openalex.org/W4384436418","https://openalex.org/W4385216645","https://openalex.org/W4386071774","https://openalex.org/W4386918841","https://openalex.org/W4387492098","https://openalex.org/W4390577857","https://openalex.org/W4390913647","https://openalex.org/W4400229079"],"related_works":[],"abstract_inverted_index":{"In":[0,27],"this":[1],"work,":[2],"we":[3,42,114],"propose":[4],"InterAxNN":[5,124,135,212],",":[6],"an":[7],"energy-aware":[8],"approximate":[9,54],"hardware":[10,120],"architecture":[11],"to":[12,29,52,74,97,122],"perform":[13,53],"vector-matrix":[14],"multiplications":[15],"in":[16,176,193,211,214],"the":[17,72,76,90,99,116,133],"binary":[18,38,55],"precision":[19,56],"regime":[20],"for":[21,37,59,108,179,183,188,195,223,231],"energy-constrained":[22],"intermittently":[23],"powered":[24],"systems":[25,60],"(IPS).":[26],"contrast":[28],"existing":[30],"XNOR":[31],"multiply-and-accumulate":[32],"(MAC)":[33],"operations":[34],"implemented":[35],"widely":[36],"neural":[39],"networks":[40],"(BNNs),":[41],"design":[43,68],"a":[44,127,151,168,201],"novel":[45],"reconfigurable":[46],"XNOR-MAC":[47,222],"and":[48,85,147,157,161,190,226,234],"AND-MAC":[49,209],"memory":[50],"macro":[51,67],"operations,":[57],"targeted":[58],"with":[61,71,150,204],"extreme":[62],"energy":[63,84,154,162],"constraints.":[64],"The":[65,208],"proposed":[66,100,134],"is":[69],"integrated":[70],"ability":[73],"modify":[75],"MAC":[77],"mode":[78,210],"during":[79],"run-time":[80],"depending":[81],"on":[82,126,200],"instantaneous":[83],"power":[86,102],"transients.":[87],"We":[88,131],"utilize":[89],"unique":[91],"attributes":[92],"of":[93,217],"ferroelectric":[94],"transistors":[95],"(FeFETs)":[96],"implement":[98,123],"ultra-low":[101],"BNN":[103],"engine":[104],"performing":[105],"in-memory":[106],"computing":[107,143],"artificial":[109],"intelligence":[110],"(AI)":[111],"workloads.":[112],"Subsequently,":[113],"leverage":[115],"quality":[117,229],"configurable":[118],"compute-in-memory-based":[119],"accelerator":[121,155],"based":[125],"TI":[128,169],"MSP430-based":[129],"microcontroller.":[130],"evaluate":[132],"concerning":[136],"two":[137],"baselines:":[138],"(a)":[139],"standard":[140],"von":[141],"Neumann":[142],"architecture-based-microcontroller":[144],"platform":[145,203],"(MCU),":[146],"(b)":[148],"MCU":[149],"state-of-the-art":[152],"low":[153],"(MCU+LEA),":[156],"observe":[158],"significant":[159],"performance":[160],"benefits.":[163],"Experimental":[164],"results":[165,213],"performed":[166],"using":[167,198],"MSP430FR5379":[170],"IPS":[171],"system":[172],"show":[173],"448\u00d7\u2013581\u00d7":[174],"uplift":[175],"forward":[177,219],"progress":[178,220],"2%\u20138%":[180],"accuracy":[181,186,194],"loss":[182,187],"MNIST,":[184,232],"4%\u20135%":[185],"EMNIST,":[189,233],"1%\u20134%":[191],"reduction":[192],"QMNIST,":[196,235],"respectively,":[197],"MLP":[199],"MCU+LEA":[202],"Unified":[205],"NVM":[206],"architecture.":[207],"91\u00d7\u2013127\u00d7":[215],"amount":[216],"additional":[218],"over":[221],"1%\u20132%,":[224],"4%\u201319%,":[225],"1%\u20135%":[227],"higher":[228],"degradation":[230],"respectively.":[236]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-13T00:00:00"}