{"id":"https://openalex.org/W7116288675","doi":"https://doi.org/10.1145/3754598.3754607","title":"ViReC: The Virtual Register Context Architecture for Efficient Near-Memory Multithreading","display_name":"ViReC: The Virtual Register Context Architecture for Efficient Near-Memory Multithreading","publication_year":2025,"publication_date":"2025-09-08","ids":{"openalex":"https://openalex.org/W7116288675","doi":"https://doi.org/10.1145/3754598.3754607"},"language":null,"primary_location":{"id":"doi:10.1145/3754598.3754607","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3754598.3754607","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th International Conference on Parallel Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3754598.3754607","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5120901795","display_name":"Matthew Barondeau","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Matthew Barondeau","raw_affiliation_strings":["The University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0009-0001-4158-5717","affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120912262","display_name":"Sophia Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sophia Jiang","raw_affiliation_strings":["The University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0009-0001-0382-9901","affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068837685","display_name":"Jonathan Curtis Beard","orcid":"https://orcid.org/0000-0002-8651-7603"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Beard","raw_affiliation_strings":["Google, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-8651-7603","affiliations":[{"raw_affiliation_string":"Google, Austin, TX, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046024226","display_name":"Andreas Gerstlauer","orcid":"https://orcid.org/0000-0002-6748-2054"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andreas Gerstlauer","raw_affiliation_strings":["The University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-6748-2054","affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5120901795"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.64401028,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"331","last_page":"341"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.4796000123023987,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.4796000123023987,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.2282000035047531,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.1054999977350235,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.8169999718666077},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.6129999756813049},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6032999753952026},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.5674999952316284},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.5006999969482422},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.438400000333786},{"id":"https://openalex.org/keywords/context-switch","display_name":"Context switch","score":0.4352000057697296},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4120999872684479},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.40459999442100525}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8633000254631042},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.8169999718666077},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.6129999756813049},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6032999753952026},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5841000080108643},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.5674999952316284},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5006999969482422},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.438400000333786},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.4352000057697296},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.41440001130104065},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4120999872684479},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.40459999442100525},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3919999897480011},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.38370001316070557},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.38339999318122864},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.3756999969482422},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.34369999170303345},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3336000144481659},{"id":"https://openalex.org/C2984984529","wikidata":"https://www.wikidata.org/wiki/Q7619925","display_name":"Storage management","level":2,"score":0.3310000002384186},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.32510000467300415},{"id":"https://openalex.org/C2778787235","wikidata":"https://www.wikidata.org/wiki/Q49007","display_name":"Yarn","level":2,"score":0.3246999979019165},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31779998540878296},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.31380000710487366},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.29899999499320984},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.2590000033378601},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.2581999897956848},{"id":"https://openalex.org/C72108876","wikidata":"https://www.wikidata.org/wiki/Q844565","display_name":"Transaction processing","level":3,"score":0.25780001282691956},{"id":"https://openalex.org/C61483411","wikidata":"https://www.wikidata.org/wiki/Q3124522","display_name":"Data parallelism","level":3,"score":0.25600001215934753}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3754598.3754607","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3754598.3754607","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th International Conference on Parallel Processing","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3754598.3754607","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3754598.3754607","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th International Conference on Parallel Processing","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1987225815","https://openalex.org/W1995140396","https://openalex.org/W2048466306","https://openalex.org/W2147657366","https://openalex.org/W2148060071","https://openalex.org/W2310426546","https://openalex.org/W2588191434","https://openalex.org/W2936567838","https://openalex.org/W3206328251","https://openalex.org/W4245021564","https://openalex.org/W4253438286","https://openalex.org/W4285113882","https://openalex.org/W4285121610","https://openalex.org/W4401328375"],"related_works":[],"abstract_inverted_index":{"Near-memory":[0],"processing":[1],"can":[2,54,76],"reduce":[3],"latency":[4],"and":[5,31,39,53],"increase":[6],"available":[7],"bandwidth":[8],"but":[9,66],"requires":[10],"extracting":[11],"memory-level":[12],"parallelism":[13,47],"under":[14],"strict":[15],"operating":[16],"constraints.":[17],"Many":[18],"memory-intensive":[19],"workloads":[20,52],"have":[21],"low":[22],"arithmetic":[23],"intensity":[24],"with":[25],"often":[26],"small":[27],"register":[28],"working":[29],"sets":[30],"memory":[32],"access":[33],"patterns":[34],"that":[35,75],"cause":[36],"frequent":[37],"stalls":[38],"poor":[40],"processor":[41],"utilization.":[42],"Latency":[43],"hiding":[44],"using":[45],"instruction-level":[46],"is":[48,60],"limited":[49],"for":[50],"such":[51],"incur":[55],"significant":[56],"overheads.":[57],"Instead,":[58],"multithreading":[59],"widely":[61],"used":[62],"to":[63],"hide":[64],"stalls,":[65],"existing":[67],"methods":[68],"use":[69],"large":[70],"statically":[71],"banked":[72],"context":[73],"storage":[74],"remain":[77],"underutilized":[78],"while":[79],"limiting":[80],"the":[81],"number":[82],"of":[83],"threads.":[84]},"counts_by_year":[],"updated_date":"2025-12-21T02:06:08.432651","created_date":"2025-12-21T00:00:00"}