{"id":"https://openalex.org/W7116560525","doi":"https://doi.org/10.1145/3750720.3757286","title":"CompressRA+: Enhanced Register Allocation for Compressed ISAs","display_name":"CompressRA+: Enhanced Register Allocation for Compressed ISAs","publication_year":2025,"publication_date":"2025-09-08","ids":{"openalex":"https://openalex.org/W7116560525","doi":"https://doi.org/10.1145/3750720.3757286"},"language":null,"primary_location":{"id":"doi:10.1145/3750720.3757286","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3750720.3757286","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Workshop Proceedings of the 54th International Conference on Parallel Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3750720.3757286","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5120873275","display_name":"Mu-Eng Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Mu-Eng Huang","raw_affiliation_strings":["Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0005-0126-6024","affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chung-Yi Chen","orcid":"https://orcid.org/0009-0005-7506-1814"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Yi Chen","raw_affiliation_strings":["Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0005-7506-1814","affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120914450","display_name":"Yi-Ping You","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Ping You","raw_affiliation_strings":["Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-4455-3147","affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5120901364","display_name":"Wuu Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wuu Yang","raw_affiliation_strings":["Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0001-8913-5662","affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5120873275"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.64714344,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"54","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9419999718666077,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9419999718666077,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.021299999207258224,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14347","display_name":"Big Data and Digital Economy","score":0.0052999998442828655,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.7042999863624573},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.6207000017166138},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5422999858856201},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5411999821662903},{"id":"https://openalex.org/keywords/addressing-mode","display_name":"Addressing mode","score":0.5174999833106995},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5026999711990356},{"id":"https://openalex.org/keywords/compression","display_name":"Compression (physics)","score":0.45179998874664307}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8252000212669373},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.7042999863624573},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.6207000017166138},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5422999858856201},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5411999821662903},{"id":"https://openalex.org/C16901944","wikidata":"https://www.wikidata.org/wiki/Q367183","display_name":"Addressing mode","level":4,"score":0.5174999833106995},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5026999711990356},{"id":"https://openalex.org/C180016635","wikidata":"https://www.wikidata.org/wiki/Q2712821","display_name":"Compression (physics)","level":2,"score":0.45179998874664307},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4390000104904175},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.42669999599456787},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3702999949455261},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3564000129699707},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.33899998664855957},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2904999852180481},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2849999964237213},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2752000093460083},{"id":"https://openalex.org/C25797200","wikidata":"https://www.wikidata.org/wiki/Q828137","display_name":"Compression ratio","level":3,"score":0.2732999920845032},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.2605000138282776},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.2549000084400177}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3750720.3757286","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3750720.3757286","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Workshop Proceedings of the 54th International Conference on Parallel Processing","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3750720.3757286","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3750720.3757286","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Workshop Proceedings of the 54th International Conference on Parallel Processing","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2035206467","https://openalex.org/W2118866757","https://openalex.org/W2501331689","https://openalex.org/W4246166885","https://openalex.org/W4321184206"],"related_works":[],"abstract_inverted_index":{"Modern":[0],"computer":[1],"architectures":[2,23,47],"are":[3],"increasingly":[4],"characterized":[5],"by":[6],"the":[7,116,144],"contrast":[8],"between":[9],"complex":[10],"instruction":[11,17,45,128],"set":[12,18,46],"computers":[13,19],"(CISC)":[14],"and":[15,26,52,100,141,165],"reduced":[16],"(RISC).":[20],"While":[21],"RISC":[22,44],"favor":[24],"simplicity":[25],"uniformity,":[27],"their":[28],"use":[29],"of":[30,111,126,158],"fixed-length":[31],"instructions":[32,56],"often":[33,96],"leads":[34],"to":[35,57,131,173],"larger":[36],"program":[37,133,155],"sizes.":[38],"To":[39],"address":[40],"this":[41,75],"issue,":[42],"some":[43],"(ISAs),":[48],"such":[49,70,92],"as":[50,93],"ARM":[51],"RISC-V,":[53],"support":[54],"compressed":[55,87,127],"reduce":[58],"code":[59,188],"size.":[60],"However,":[61],"current":[62],"approaches":[63],"primarily":[64],"rely":[65],"on":[66,139,160,167],"post-compilation":[67,192],"compression,":[68],"overlooking":[69],"opportunities":[71],"during":[72],"compilation.":[73],"In":[74],"paper,":[76],"we":[77],"propose":[78],"CompressRA+,":[79],"a":[80,108],"register":[81,104,117,183],"allocation":[82,118,184],"algorithm":[83],"explicitly":[84],"designed":[85],"for":[86],"ISAs.":[88],"Unlike":[89],"prior":[90],"work,":[91],"CompressRA,":[94],"which":[95],"overestimates":[97],"potential":[98],"compressibility":[99],"results":[101,148,176],"in":[102],"suboptimal":[103],"assignments,":[105],"CompressRA+":[106,138,151],"incorporates":[107],"precise":[109],"analysis":[110],"compression":[112,180,193],"feasibility":[113],"directly":[114],"within":[115],"phase.":[119],"This":[120],"integration":[121],"enables":[122],"more":[123,132],"effective":[124],"utilization":[125],"encodings,":[129],"leading":[130],"size":[134,156,189],"reductions.":[135],"We":[136],"evaluated":[137],"Polybench":[140,161],"SPEC2017,":[142],"targeting":[143],"RISC-V":[145],"architecture.":[146],"Experimental":[147],"show":[149],"that":[150,178],"achieved":[152],"an":[153],"average":[154],"reduction":[157],"0.89%":[159],"(1.64%":[162],"at":[163,170],"most)":[164,171],"0.3%":[166],"SPEC2017":[168],"(1.71%":[169],"compared":[172],"CompressRA.":[174],"The":[175],"demonstrate":[177],"integrating":[179],"awareness":[181],"into":[182],"can":[185],"unlock":[186],"additional":[187],"reductions":[190],"beyond":[191],"techniques.":[194]},"counts_by_year":[],"updated_date":"2026-04-25T08:17:42.794288","created_date":"2025-12-21T00:00:00"}
