{"id":"https://openalex.org/W7127999123","doi":"https://doi.org/10.1145/3748173.3779573","title":"MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage","display_name":"MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage","publication_year":2026,"publication_date":"2026-02-05","ids":{"openalex":"https://openalex.org/W7127999123","doi":"https://doi.org/10.1145/3748173.3779573"},"language":null,"primary_location":{"id":"doi:10.1145/3748173.3779573","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779573","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3748173.3779573","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5125208425","display_name":"Tarun Kholay","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tarun Kholay","raw_affiliation_strings":["The University of Texas at Austin, Austin, Texas, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, Texas, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119867907","display_name":"Anup Ashok Kedilaya","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anup Ashok Kedilaya","raw_affiliation_strings":["The University of Texas at Austin, Austin, Texas, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, Texas, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045858420","display_name":"Aman Arora","orcid":"https://orcid.org/0000-0003-2547-4424"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aman Arora","raw_affiliation_strings":["Arizona State University, Phoenix, Arizona, USA"],"affiliations":[{"raw_affiliation_string":"Arizona State University, Phoenix, Arizona, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jaydeep P. Kulkarni","orcid":"https://orcid.org/0000-0002-0258-6776"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaydeep P. Kulkarni","raw_affiliation_strings":["The University of Texas at Austin, Austin, Texas, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, Texas, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125233562","display_name":"Lizy K. John","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lizy K. John","raw_affiliation_strings":["The University of Texas at Austin, Austin, Texas, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, Austin, Texas, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5125208425"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.25220938,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"144","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.46299999952316284,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.46299999952316284,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.43380001187324524,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.02019999921321869,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.901199996471405},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8880000114440918},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.6380000114440918},{"id":"https://openalex.org/keywords/estimation","display_name":"Estimation","score":0.598800003528595},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5651999711990356},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5382000207901001}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.901199996471405},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8880000114440918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6779000163078308},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.6380000114440918},{"id":"https://openalex.org/C96250715","wikidata":"https://www.wikidata.org/wiki/Q965330","display_name":"Estimation","level":2,"score":0.598800003528595},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5753999948501587},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5651999711990356},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5382000207901001},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4715999960899353},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.45840001106262207},{"id":"https://openalex.org/C29202148","wikidata":"https://www.wikidata.org/wiki/Q287260","display_name":"Resource allocation","level":2,"score":0.38370001316070557},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3598000109195709},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.352400004863739},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.30720001459121704},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.289000004529953},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2791999876499176}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3748173.3779573","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779573","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3748173.3779573","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779573","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"FPGA":[0,38,91,139],"design":[1,21,96],"evaluation":[2],"faces":[3],"significant":[4],"challenges":[5],"due":[6],"to":[7,73],"heterogeneous":[8],"resource":[9],"reporting":[10],"across":[11,89],"vendors":[12],"and":[13,19,39,57,102,130],"architectures,":[14],"which":[15],"hinders":[16],"performance":[17],"comparisons":[18],"complicates":[20],"space":[22,97],"exploration.":[23],"We":[24],"present":[25],"MARU":[26,48,115],"(Machine-learning":[27],"for":[28,111,127,134],"Area":[29],"estimation":[30,42,68,88],"from":[31,44,70],"Resource":[32],"Usage),":[33],"a":[34,50,124,131],"framework":[35,80,126],"that":[36],"enables":[37,81],"ASIC":[40,104,143],"area":[41,110,148],"directly":[43],"HLS":[45,95],"utilization":[46],"reports.":[47],"achieves":[49],"mean":[51],"absolute":[52],"percentage":[53],"error":[54],"of":[55,60],"1.5%":[56],"an":[58],"R\u00b2":[59],"0.997":[61],"in":[62],"cross-FPGA,":[63],"multi-circuit":[64],"predictions,":[65],"while":[66],"reducing":[67],"time":[69],"2.5":[71],"days":[72],"just":[74],"5":[75],"minutes":[76],"per":[77],"design.":[78],"The":[79],"three":[82],"key":[83],"advancements:":[84],"1)":[85],"unified,":[86],"area-based":[87],"diverse":[90],"designs,":[92],"2)":[93],"accelerated":[94],"exploration":[98],"through":[99,146],"real-time":[100],"prediction,":[101],"3)":[103],"migration":[105],"analysis":[106],"by":[107,121],"estimating":[108],"equivalent":[109],"predictive":[112,147],"cost":[113],"modeling.":[114,149],"bridges":[116],"the":[117],"FPGA/ASIC":[118],"methodology":[119],"gap":[120],"providing":[122],"both":[123],"comparative":[125],"academic":[128],"research":[129],"practical":[132],"tool":[133],"industry-scale":[135],"co-design":[136],"decisions\u2014whether":[137],"optimizing":[138],"implementations":[140],"or":[141],"evaluating":[142],"transition":[144],"feasibility":[145]},"counts_by_year":[],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2026-02-07T00:00:00"}
