{"id":"https://openalex.org/W7127978444","doi":"https://doi.org/10.1145/3748173.3779570","title":"Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture","display_name":"Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture","publication_year":2026,"publication_date":"2026-02-05","ids":{"openalex":"https://openalex.org/W7127978444","doi":"https://doi.org/10.1145/3748173.3779570"},"language":null,"primary_location":{"id":"doi:10.1145/3748173.3779570","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779570","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3748173.3779570","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057468423","display_name":"Ryo Iwasaki","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Ryo Iwasaki","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125112635","display_name":"Tatsuya Sasaki","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tatsuya Sasaki","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022270675","display_name":"Yumi ISEKI","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yumi Iseki","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125135046","display_name":"Sota Kohata","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Sota Kohata","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112335286","display_name":"Miyu Yoshida","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Miyu Yoshida","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125210004","display_name":"Kenshu Seto","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenshu Seto","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010462341","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9897-6073"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5057468423"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.69016073,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"181","last_page":"181"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8277999758720398,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8277999758720398,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.09570000320672989,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.021400000900030136,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5813000202178955},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.47850000858306885},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.45750001072883606},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4390000104904175},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4043000042438507},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.36010000109672546},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35910001397132874},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.3163999915122986},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.30489999055862427}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6854000091552734},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5813000202178955},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.47850000858306885},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.45750001072883606},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4390000104904175},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42570000886917114},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4043000042438507},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.39660000801086426},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.36629998683929443},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.36010000109672546},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35910001397132874},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3483999967575073},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.3163999915122986},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.30489999055862427},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.29760000109672546},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.29319998621940613},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.29109999537467957},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.2808000147342682},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.28060001134872437},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.2655999958515167},{"id":"https://openalex.org/C87044965","wikidata":"https://www.wikidata.org/wiki/Q1091139","display_name":"Enhanced Interior Gateway Routing Protocol","level":5,"score":0.2655999958515167},{"id":"https://openalex.org/C76522221","wikidata":"https://www.wikidata.org/wiki/Q5035396","display_name":"Multipath routing","level":5,"score":0.2632000148296356},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.2632000148296356},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.26100000739097595},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.2590999901294708},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.2572999894618988},{"id":"https://openalex.org/C2984173633","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Routing algorithm","level":4,"score":0.2554999887943268},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.25279998779296875},{"id":"https://openalex.org/C89305328","wikidata":"https://www.wikidata.org/wiki/Q1755411","display_name":"Link-state routing protocol","level":4,"score":0.25029999017715454}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3748173.3779570","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779570","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3748173.3779570","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779570","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[{"score":0.7740970253944397,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"We":[0],"address":[1],"the":[2,10,29,38],"area":[3,47],"overhead":[4],"of":[5],"synthesizable":[6],"eFPGAs":[7],"by":[8,48],"proposing":[9],"''PAE":[11],"Cell,''":[12],"an":[13],"AIG-based":[14],"multi-output":[15],"logic":[16],"cell,":[17],"and":[18],"a":[19],"domain-specific":[20],"routing":[21,42],"architecture":[22,43],"for":[23],"control":[24],"logic.":[25],"Evaluations":[26],"demonstrate":[27],"that":[28],"PAE":[30],"Cell":[31],"achieves":[32],"4-LUT":[33],"equivalence":[34],"at":[35],"approximately":[36],"0.4\u00d7":[37],"area,":[39],"while":[40],"our":[41],"reduces":[44],"total":[45],"eFPGA":[46],"up":[49],"to":[50,53],"80%":[51],"compared":[52],"conventional":[54],"islandstyle":[55],"designs.":[56]},"counts_by_year":[],"updated_date":"2026-02-20T08:17:22.645390","created_date":"2026-02-07T00:00:00"}