{"id":"https://openalex.org/W7127976653","doi":"https://doi.org/10.1145/3748173.3779199","title":"TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement","display_name":"TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement","publication_year":2026,"publication_date":"2026-02-05","ids":{"openalex":"https://openalex.org/W7127976653","doi":"https://doi.org/10.1145/3748173.3779199"},"language":null,"primary_location":{"id":"doi:10.1145/3748173.3779199","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779199","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3748173.3779199","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100639356","display_name":"Jiarui Wang","orcid":"https://orcid.org/0000-0002-7054-384X"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiarui Wang","raw_affiliation_strings":["School of Computer Science, Peking University, Beijing, Beijing, China and School of Integrated Circuits, Peking University, Beijing, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-7054-384X","affiliations":[{"raw_affiliation_string":"School of Computer Science, Peking University, Beijing, Beijing, China and School of Integrated Circuits, Peking University, Beijing, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014230059","display_name":"Runzhe Tao","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Runzhe Tao","raw_affiliation_strings":["School of Integrated Circuits, Peking University, Beijing, Beijing, China"],"raw_orcid":"https://orcid.org/0009-0003-1135-5667","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Peking University, Beijing, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042195167","display_name":"Jing Mai","orcid":"https://orcid.org/0000-0002-3787-1534"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Mai","raw_affiliation_strings":["School of Computer Science, Peking University, Beijing, Beijing, China and School of Integrated Circuits, Peking University, Beijing, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-3787-1534","affiliations":[{"raw_affiliation_string":"School of Computer Science, Peking University, Beijing, Beijing, China and School of Integrated Circuits, Peking University, Beijing, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Xun Jiang","orcid":"https://orcid.org/0009-0006-7958-8485"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xun Jiang","raw_affiliation_strings":["School of Integrated Circuits, Peking University, Beijing, Beijing, China"],"raw_orcid":"https://orcid.org/0009-0006-7958-8485","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Peking University, Beijing, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125147458","display_name":"Shenghua Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089559","display_name":"Shenzhen Metro (China)","ror":"https://ror.org/008hpge95","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210089559"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shenghua Wang","raw_affiliation_strings":["S2C Inc., Shenzhen, Guangdong, China"],"raw_orcid":"https://orcid.org/0000-0002-8138-1911","affiliations":[{"raw_affiliation_string":"S2C Inc., Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I4210089559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016972939","display_name":"Cuiliu Yang","orcid":"https://orcid.org/0000-0002-7577-329X"},"institutions":[{"id":"https://openalex.org/I4210089559","display_name":"Shenzhen Metro (China)","ror":"https://ror.org/008hpge95","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210089559"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Cuiliu Yang","raw_affiliation_strings":["S2C Inc., Shenzhen, Guangdong, China"],"raw_orcid":"https://orcid.org/0000-0002-7577-329X","affiliations":[{"raw_affiliation_string":"S2C Inc., Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I4210089559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125141287","display_name":"Haoyu Jie","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089559","display_name":"Shenzhen Metro (China)","ror":"https://ror.org/008hpge95","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210089559"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haoyu Jie","raw_affiliation_strings":["S2C Inc., Shenzhen, Guangdong, China"],"raw_orcid":"https://orcid.org/0009-0004-8792-8537","affiliations":[{"raw_affiliation_string":"S2C Inc., Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I4210089559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101705671","display_name":"Kan Huang","orcid":"https://orcid.org/0000-0003-0242-0116"},"institutions":[{"id":"https://openalex.org/I4210089559","display_name":"Shenzhen Metro (China)","ror":"https://ror.org/008hpge95","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210089559"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kan Huang","raw_affiliation_strings":["S2C Inc., Shenzhen, Guangdong, China"],"raw_orcid":"https://orcid.org/0000-0003-0242-0116","affiliations":[{"raw_affiliation_string":"S2C Inc., Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I4210089559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111879691","display_name":"Richard Y. Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089559","display_name":"Shenzhen Metro (China)","ror":"https://ror.org/008hpge95","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210089559"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Richard Y. Sun","raw_affiliation_strings":["S2C Inc., Shenzhen, Guangdong, China"],"raw_orcid":"https://orcid.org/0009-0003-3924-2154","affiliations":[{"raw_affiliation_string":"S2C Inc., Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I4210089559"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000933188","display_name":"Yibo Lin","orcid":"https://orcid.org/0000-0002-0977-2774"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yibo Lin","raw_affiliation_strings":["School of Integrated Circuits, Peking University, Beijing, Beijing, China, Institute of EDA, Peking University, Beijing, Beijing, China, and Advanced Innovation Center for Integrated Circuits, Beijing, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-0977-2774","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Peking University, Beijing, Beijing, China, Institute of EDA, Peking University, Beijing, Beijing, China, and Advanced Innovation Center for Integrated Circuits, Beijing, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14507194,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"201","last_page":"211"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9830999970436096,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9830999970436096,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.008500000461935997,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0017999999690800905,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7947999835014343},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5648000240325928},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5414000153541565},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5016000270843506},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4300000071525574},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.39079999923706055},{"id":"https://openalex.org/keywords/retard","display_name":"Retard","score":0.34549999237060547},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.3440999984741211}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7947999835014343},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7343000173568726},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5648000240325928},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5414000153541565},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5016000270843506},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.47209998965263367},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4300000071525574},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3928000032901764},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.39079999923706055},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34869998693466187},{"id":"https://openalex.org/C2777131613","wikidata":"https://www.wikidata.org/wiki/Q18394147","display_name":"Retard","level":2,"score":0.34549999237060547},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3440999984741211},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.3418000042438507},{"id":"https://openalex.org/C2778820799","wikidata":"https://www.wikidata.org/wiki/Q3454688","display_name":"Cost reduction","level":2,"score":0.3230000138282776},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3084999918937683},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.30239999294281006},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.29789999127388},{"id":"https://openalex.org/C195563490","wikidata":"https://www.wikidata.org/wiki/Q180368","display_name":"Network congestion","level":3,"score":0.295199990272522},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2906000018119812},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2849999964237213},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2766999900341034},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.274399995803833},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2635999917984009},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.26339998841285706},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.25380000472068787},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.250900000333786}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3748173.3779199","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779199","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3748173.3779199","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779199","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2148658001","https://openalex.org/W2884307971","https://openalex.org/W3034996971","https://openalex.org/W3036696276","https://openalex.org/W4386523879","https://openalex.org/W4389919621","https://openalex.org/W4401414256"],"related_works":[],"abstract_inverted_index":{"Large-scale":[0],"multi-FPGA":[1,16,133],"systems":[2],"are":[3],"widely":[4],"used":[5],"in":[6,34],"modern":[7],"emulation":[8],"systems.":[9],"As":[10],"a":[11,66,108,127],"critical":[12],"part":[13],"of":[14],"the":[15,29,35,49],"system":[17],"design":[18],"flow,":[19],"TDM":[20],"signal":[21,87],"grouping":[22,88],"and":[23,32,45,89,112],"package":[24],"pin":[25,40,68,90],"assignment":[26,69],"directly":[27],"impact":[28],"final":[30],"placement":[31,73,91],"routing":[33],"FPGA":[36],"physical":[37,80],"implementation.":[38],"Poor":[39],"assignments":[41],"cause":[42],"severe":[43],"congestion":[44,57,78,110],"timing":[46],"degradation":[47],"at":[48],"logic-element":[50],"level,":[51],"while":[52,125],"existing":[53],"approaches":[54],"lack":[55],"accurate":[56],"modeling":[58],"during":[59],"system-level":[60],"partitioning.":[61],"This":[62],"paper":[63],"presents":[64],"Chimew,":[65],"novel":[67],"methodology":[70],"that":[71],"leverages":[72],"prototyping":[74],"to":[75,114,122],"predict":[76],"logic-element-level":[77],"before":[79],"implementation":[81],"precisely.":[82],"The":[83],"proposed":[84],"method":[85],"co-optimizes":[86],"through":[92],"iterative":[93],"refinement":[94],"guided":[95],"by":[96],"congestion-aware":[97],"cost":[98],"functions":[99],"derived":[100],"from":[101],"fast":[102],"global":[103],"placement.":[104],"Experimental":[105],"results":[106],"demonstrate":[107],"28%":[109],"reduction":[111],"up":[113],"2.87ns":[115],"less":[116],"worst":[117],"negative":[118],"slack":[119],"(WNS)":[120],"compared":[121],"industrial":[123],"tools":[124],"achieving":[126],"100%":[128],"success":[129],"rate":[130],"across":[131],"diverse":[132],"benchmarks.":[134]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-02-07T00:00:00"}