{"id":"https://openalex.org/W7127964067","doi":"https://doi.org/10.1145/3748173.3779188","title":"CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving","display_name":"CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving","publication_year":2026,"publication_date":"2026-02-05","ids":{"openalex":"https://openalex.org/W7127964067","doi":"https://doi.org/10.1145/3748173.3779188"},"language":null,"primary_location":{"id":"doi:10.1145/3748173.3779188","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779188","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3748173.3779188","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5125178516","display_name":"Dong Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I32971472","display_name":"Yale University","ror":"https://ror.org/03v76x132","country_code":"US","type":"education","lineage":["https://openalex.org/I32971472"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dong Liu","raw_affiliation_strings":["Yale University, New Haven, Connecticut, USA"],"raw_orcid":"https://orcid.org/0009-0009-6815-8297","affiliations":[{"raw_affiliation_string":"Yale University, New Haven, Connecticut, USA","institution_ids":["https://openalex.org/I32971472"]}]},{"author_position":"last","author":{"id":null,"display_name":"Yanxuan Yu","orcid":"https://orcid.org/0009-0001-7096-2438"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yanxuan Yu","raw_affiliation_strings":["Columbia University, New York, New York, USA"],"raw_orcid":"https://orcid.org/0009-0001-7096-2438","affiliations":[{"raw_affiliation_string":"Columbia University, New York, New York, USA","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":54.0488,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.99954853,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"56","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.322299987077713,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.322299987077713,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10181","display_name":"Natural Language Processing Techniques","score":0.21220000088214874,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.04749999940395355,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5024999976158142},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.4535999894142151},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.44029998779296875},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.43230000138282776},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4244999885559082},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.42340001463890076},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.39489999413490295},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.38960000872612},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.37380000948905945},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.3700999915599823}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8205999732017517},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6029999852180481},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5024999976158142},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.4535999894142151},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.44029998779296875},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.43230000138282776},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4244999885559082},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.42340001463890076},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.39489999413490295},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.38960000872612},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3756999969482422},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.37380000948905945},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.3700999915599823},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.3700000047683716},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.36230000853538513},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.36039999127388},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.3538999855518341},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.3481000065803528},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.3474000096321106},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.34700000286102295},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3449000120162964},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.3328999876976013},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.33219999074935913},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.32749998569488525},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3206000030040741},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3163999915122986},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.31520000100135803},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.2985000014305115},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.29260000586509705},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2791999876499176},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.2727000117301941},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.27160000801086426},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.2703999876976013},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.27000001072883606},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.2671000063419342},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.26249998807907104},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.2590999901294708},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.25870001316070557},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.25850000977516174},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25760000944137573}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3748173.3779188","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779188","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3748173.3779188","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779188","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2094756095","https://openalex.org/W2276486856","https://openalex.org/W2963929190","https://openalex.org/W4254778370","https://openalex.org/W4387321091","https://openalex.org/W4407953517","https://openalex.org/W4415536372"],"related_works":[],"abstract_inverted_index":{"Large":[0],"Language":[1],"Models":[2],"(LLMs)":[3],"have":[4],"revolutionized":[5],"natural":[6],"language":[7],"processing":[8],"tasks,":[9],"but":[10],"their":[11],"deployment":[12],"in":[13,175],"datacenter":[14],"environments":[15],"faces":[16],"significant":[17],"challenges":[18],"due":[19],"to":[20,69,92,129,140,145],"the":[21,30,171],"massive":[22],"memory":[23,75,86,95,124,150,162,172],"requirements":[24,126],"of":[25],"key-value":[26],"(KV)":[27],"caches.":[28],"During":[29],"autoregressive":[31],"decoding":[32],"process,":[33],"KV":[34],"caches":[35],"consume":[36],"substantial":[37],"GPU":[38],"memory,":[39],"limiting":[40],"batch":[41],"sizes":[42],"and":[43,66,74,107,113,119,154],"overall":[44],"system":[45,158],"throughput.":[46],"To":[47],"address":[48,170],"these":[49],"challenges,":[50],"we":[51],"propose":[52],"CXL-SpecKV,":[53],"a":[54,84,100],"novel":[55],"disaggregated":[56],"KV-cache":[57,102,117],"architecture":[58],"that":[59,89,105,122,160],"leverages":[60],"Compute":[61],"Express":[62],"Link":[63],"(CXL)":[64],"interconnects":[65],"FPGA":[67,94],"accelerators":[68],"enable":[70],"efficient":[71],"speculative":[72,101,166],"execution":[73,167],"disaggregation.":[76],"Our":[77,157],"approach":[78],"introduces":[79],"three":[80],"key":[81],"innovations:":[82],"(i)":[83],"CXL-based":[85],"disaggregation":[87,163],"framework":[88],"offloads":[90],"KV-caches":[91],"remote":[93],"with":[96,165],"low":[97],"latency,":[98],"(ii)":[99],"prefetching":[103],"mechanism":[104],"predicts":[106],"preloads":[108],"future":[109],"tokens'":[110],"cache":[111],"entries,":[112],"(iii)":[114],"an":[115],"FPGA-accelerated":[116],"compression":[118],"decompression":[120],"engine":[121],"reduces":[123],"bandwidth":[125],"by":[127,152],"up":[128,139],"4\u00d7.":[130],"When":[131],"evaluated":[132],"on":[133],"state-of-the-art":[134],"LLM":[135,177],"models,":[136],"CXL-SpecKV":[137],"achieves":[138],"3.2\u00d7":[141],"higher":[142],"throughput":[143],"compared":[144],"GPU-only":[146],"baselines,":[147],"while":[148],"reducing":[149],"costs":[151],"2.8\u00d7":[153],"maintaining":[155],"accuracy.":[156],"demonstrates":[159],"intelligent":[161],"combined":[164],"can":[168],"effectively":[169],"wall":[173],"challenge":[174],"large-scale":[176],"serving.":[178]},"counts_by_year":[{"year":2026,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-02-07T00:00:00"}