{"id":"https://openalex.org/W7127909770","doi":"https://doi.org/10.1145/3748173.3779186","title":"RND: A Mixed-Grained Parallel Routing Framework with <u>R</u> egion-based <u>N</u> et <u>D</u> ecomposition for UltraScale FPGAs","display_name":"RND: A Mixed-Grained Parallel Routing Framework with <u>R</u> egion-based <u>N</u> et <u>D</u> ecomposition for UltraScale FPGAs","publication_year":2026,"publication_date":"2026-02-05","ids":{"openalex":"https://openalex.org/W7127909770","doi":"https://doi.org/10.1145/3748173.3779186"},"language":null,"primary_location":{"id":"doi:10.1145/3748173.3779186","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779186","pdf_url":null,"source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3748173.3779186","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020755860","display_name":"Wenhao Lin","orcid":"https://orcid.org/0009-0007-3189-7868"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Wenhao Lin","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125100940","display_name":"Zewen Li","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Zewen Li","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037988878","display_name":"Xinshi Zang","orcid":"https://orcid.org/0009-0002-7889-4481"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Xinshi Zang","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125133314","display_name":"Evangeline F.Y. Young","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Evangeline F.Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong, Shatin, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Shatin, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5020755860"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.34679593,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"12","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9735999703407288,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9735999703407288,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.010999999940395355,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.005200000014156103,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7785999774932861},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6735000014305115},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5885999798774719},{"id":"https://openalex.org/keywords/multipath-routing","display_name":"Multipath routing","score":0.4146000146865845},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4041000008583069},{"id":"https://openalex.org/keywords/disjoint-sets","display_name":"Disjoint sets","score":0.3488999903202057},{"id":"https://openalex.org/keywords/metrics","display_name":"Metrics","score":0.33820000290870667},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.32350000739097595}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7785999774932861},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.765500009059906},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6735000014305115},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5885999798774719},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5759000182151794},{"id":"https://openalex.org/C76522221","wikidata":"https://www.wikidata.org/wiki/Q5035396","display_name":"Multipath routing","level":5,"score":0.4146000146865845},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4041000008583069},{"id":"https://openalex.org/C45340560","wikidata":"https://www.wikidata.org/wiki/Q215382","display_name":"Disjoint sets","level":2,"score":0.3488999903202057},{"id":"https://openalex.org/C195780805","wikidata":"https://www.wikidata.org/wiki/Q1535986","display_name":"Metrics","level":5,"score":0.33820000290870667},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.32350000739097595},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.3109000027179718},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.30880001187324524},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3082999885082245},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.3001999855041504},{"id":"https://openalex.org/C2984173633","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Routing algorithm","level":4,"score":0.29490000009536743},{"id":"https://openalex.org/C74294265","wikidata":"https://www.wikidata.org/wiki/Q506273","display_name":"Circuit switching","level":2,"score":0.2687999904155731},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.26840001344680786},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.26570001244544983},{"id":"https://openalex.org/C115443555","wikidata":"https://www.wikidata.org/wiki/Q5367790","display_name":"Equal-cost multi-path routing","level":5,"score":0.2621999979019165},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.25999999046325684},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.25369998812675476}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3748173.3779186","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779186","pdf_url":null,"source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3748173.3779186","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3748173.3779186","pdf_url":null,"source":null,"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1983241261","https://openalex.org/W1999074645","https://openalex.org/W2105917387","https://openalex.org/W2181150664","https://openalex.org/W2275304190","https://openalex.org/W2583892184","https://openalex.org/W2792745633","https://openalex.org/W2891839221","https://openalex.org/W2905090969","https://openalex.org/W2915693550","https://openalex.org/W2950858046","https://openalex.org/W3013952364","https://openalex.org/W3033033241","https://openalex.org/W4236407101","https://openalex.org/W4249043400","https://openalex.org/W4286655084","https://openalex.org/W4367050909","https://openalex.org/W4389166655","https://openalex.org/W4403278520","https://openalex.org/W4413278532"],"related_works":[],"abstract_inverted_index":{"As":[0],"the":[1,18,35,49,88,97,104,122,132],"size":[2],"of":[3,39,52],"circuit":[4,19,41],"designs":[5],"continues":[6],"to":[7,16,31,59,66],"grow,":[8],"it":[9,64],"has":[10],"long":[11],"been":[12,29],"a":[13,75],"significant":[14],"challenge":[15],"accelerate":[17],"compilation":[20],"flow":[21],"for":[22,136,147],"modern":[23,56],"FPGAs.":[24,138],"Many":[25],"parallel":[26,78],"algorithms":[27],"have":[28],"proposed":[30,111],"speed":[32],"up":[33],"routing,":[34],"most":[36],"time-consuming":[37],"stage":[38],"FPGA":[40,77,89,105],"compilation,":[42],"by":[43,86],"leveraging":[44],"more":[45],"computing":[46],"resources.":[47],"However,":[48],"high":[50,68],"density":[51],"net":[53],"distribution":[54],"in":[55],"FPGAs":[57],"leads":[58],"severe":[60],"data":[61],"conflicts,":[62],"making":[63],"difficult":[65],"achieve":[67],"parallelism.":[69],"In":[70,103],"this":[71],"work,":[72],"we":[73],"propose":[74],"mixed-grained":[76],"routing":[79,90,107,145],"framework,":[80],"RND,":[81],"which":[82],"implements":[83],"task":[84],"decoupling":[85],"dividing":[87],"graph":[91],"into":[92,100],"disjoint":[93],"regions":[94],"and":[95,126],"decomposing":[96],"signal":[98],"nets":[99],"in-region":[101],"connections.":[102],"2024":[106],"contest":[108],"benchmarks,":[109],"our":[110,140],"router":[112,124,135,141],"achieves":[113],"an":[114],"average":[115],"5.41\u00d7":[116],"speedup":[117],"with":[118],"32":[119],"threads":[120],"over":[121],"serial":[123],"RWRoute":[125],"is":[127],"26.7%":[128],"faster":[129],"than":[130],"Potter-S,":[131],"fastest":[133],"deterministic":[134],"UltraScale":[137],"Meanwhile,":[139],"does":[142],"not":[143],"sacrifice":[144],"quality":[146],"acceleration.":[148]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2026-02-07T00:00:00"}
