{"id":"https://openalex.org/W7111099953","doi":"https://doi.org/10.1145/3742873.3755990","title":"Extending a RISC-V Core with Sub-FP8 Support for Machine Learning","display_name":"Extending a RISC-V Core with Sub-FP8 Support for Machine Learning","publication_year":2025,"publication_date":"2025-09-28","ids":{"openalex":"https://openalex.org/W7111099953","doi":"https://doi.org/10.1145/3742873.3755990"},"language":null,"primary_location":{"id":"doi:10.1145/3742873.3755990","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3742873.3755990","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3742873.3755990","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3742873.3755990","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Kathryn Chapman","orcid":"https://orcid.org/0009-0005-6986-8144"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kathryn Chapman","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0005-6986-8144","affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Fu-Jian Shen","orcid":"https://orcid.org/0009-0007-8057-642X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Fu-Jian Shen","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0007-8057-642X","affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jhih-Kuan Lin","orcid":"https://orcid.org/0009-0001-9559-6059"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jhih-Kuan Lin","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0001-9559-6059","affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":null,"display_name":"Jenq-Kuen Lee","orcid":"https://orcid.org/0000-0001-9919-6258"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jenq-Kuen Lee","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0001-9919-6258","affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.58037621,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"15","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6794000267982483,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6794000267982483,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.15360000729560852,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14347","display_name":"Big Data and Digital Economy","score":0.07769999653100967,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.9570000171661377},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6603000164031982},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.5214999914169312},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4577000141143799},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4388999938964844},{"id":"https://openalex.org/keywords/extension","display_name":"Extension (predicate logic)","score":0.4009000062942505},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.3937999904155731},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.3702000081539154},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.36149999499320984}],"concepts":[{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.9570000171661377},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8313000202178955},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6603000164031982},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.5214999914169312},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.5167999863624573},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.49970000982284546},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4577000141143799},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4388999938964844},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.4009000062942505},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.3937999904155731},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.38359999656677246},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.3702000081539154},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.36149999499320984},{"id":"https://openalex.org/C34585555","wikidata":"https://www.wikidata.org/wiki/Q1368723","display_name":"Learning curve","level":2,"score":0.3569999933242798},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3149000108242035},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2976999878883362},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29670000076293945},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.29660001397132874},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.29649999737739563},{"id":"https://openalex.org/C137981799","wikidata":"https://www.wikidata.org/wiki/Q1369184","display_name":"Reusability","level":3,"score":0.29440000653266907},{"id":"https://openalex.org/C157170001","wikidata":"https://www.wikidata.org/wiki/Q4781507","display_name":"Applications of artificial intelligence","level":2,"score":0.29159998893737793},{"id":"https://openalex.org/C12267149","wikidata":"https://www.wikidata.org/wiki/Q282453","display_name":"Support vector machine","level":2,"score":0.2912999987602234},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.28519999980926514},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2808000147342682},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.2775999903678894},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27730000019073486},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.2768000066280365},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.27309998869895935},{"id":"https://openalex.org/C8797682","wikidata":"https://www.wikidata.org/wiki/Q2115","display_name":"XML","level":2,"score":0.2644999921321869},{"id":"https://openalex.org/C50292564","wikidata":"https://www.wikidata.org/wiki/Q2462783","display_name":"Computational learning theory","level":3,"score":0.2572999894618988},{"id":"https://openalex.org/C51632099","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Training set","level":2,"score":0.2547999918460846},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.25380000472068787}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3742873.3755990","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3742873.3755990","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3742873.3755990","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3742873.3755990","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3742873.3755990","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3742873.3755990","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6256861686706543,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7111099953.pdf","grobid_xml":"https://content.openalex.org/works/W7111099953.grobid-xml"},"referenced_works_count":4,"referenced_works":["https://openalex.org/W2147657366","https://openalex.org/W2798846955","https://openalex.org/W4300013637","https://openalex.org/W4307922031"],"related_works":[],"abstract_inverted_index":{"Modern":[0],"deep":[1],"learning":[2],"workloads":[3],"demand":[4],"massive":[5],"computational":[6],"resources,":[7],"making":[8],"energy-efficient":[9],"computing":[10],"paradigms":[11],"essential.":[12],"Currently,":[13],"compiler":[14],"and":[15,26,48,77,115],"hardware":[16,49,68],"support":[17,111],"for":[18,42,90,112],"emerging":[19],"formats":[20],"like":[21],"FP8":[22,91],"(E5M2/E4M3),":[23],"FP6":[24],"(E3M2/E2M3),":[25],"FP4":[27],"remain":[28],"limited":[29],"in":[30,81],"the":[31,59],"RISC-V":[32],"ecosystem.":[33],"This":[34],"paper":[35],"presents":[36],"a":[37,103,108],"scalar":[38],"sub-FP8":[39,104],"ISA":[40],"extension":[41],"RISC-V,":[43],"with":[44,107],"full":[45],"LLVM":[46],"toolchain":[47],"support.":[50],"Our":[51],"design":[52],"decouples":[53],"format":[54,63],"specification":[55],"from":[56],"instructions":[57],"using":[58,70],"fcsr":[60],"to":[61],"store":[62],"information.":[64],"Post-synthesis":[65],"evaluation":[66],"confirms":[67],"efficiency,":[69],"only":[71],"an":[72],"increase":[73],"of":[74],"0.9%":[75],"registers":[76],"2.3%":[78],"additional":[79],"LUTs":[80],"CVA6,":[82],"while":[83],"delivering":[84],"20\u00d7":[85],"lower":[86],"cache":[87],"miss":[88],"rates":[89],"GEMM":[92],"versus":[93],"FP32":[94],"operations.":[95],"In":[96],"addition,":[97],"we":[98],"introduce":[99],"future":[100],"work":[101],"on":[102,110],"vector":[105],"extension,":[106],"focus":[109],"FP8,":[113],"FP6,":[114],"FP4.":[116]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-12-10T00:00:00"}