{"id":"https://openalex.org/W4409211728","doi":"https://doi.org/10.1145/3728467","title":"Optimizing FPGA Routing with Explainable Co-Learning of Congestion and Wirelength","display_name":"Optimizing FPGA Routing with Explainable Co-Learning of Congestion and Wirelength","publication_year":2025,"publication_date":"2025-04-07","ids":{"openalex":"https://openalex.org/W4409211728","doi":"https://doi.org/10.1145/3728467"},"language":"en","primary_location":{"id":"doi:10.1145/3728467","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3728467","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Wenhao Liu","orcid":"https://orcid.org/0009-0000-5816-0099"},"institutions":[{"id":"https://openalex.org/I139024713","display_name":"Guangdong University of Technology","ror":"https://ror.org/04azbjn80","country_code":"CN","type":"education","lineage":["https://openalex.org/I139024713"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenhao Liu","raw_affiliation_strings":["School of Integrated Circuits, School of Automation, Guangdong University of Technology, Guangzhou, China"],"raw_orcid":"https://orcid.org/0009-0000-5816-0099","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, School of Automation, Guangdong University of Technology, Guangzhou, China","institution_ids":["https://openalex.org/I139024713"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037184264","display_name":"Yan Xing","orcid":"https://orcid.org/0000-0001-7651-5287"},"institutions":[{"id":"https://openalex.org/I139024713","display_name":"Guangdong University of Technology","ror":"https://ror.org/04azbjn80","country_code":"CN","type":"education","lineage":["https://openalex.org/I139024713"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yan Xing","raw_affiliation_strings":["School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"],"raw_orcid":"https://orcid.org/0000-0001-7651-5287","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China","institution_ids":["https://openalex.org/I139024713"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050076555","display_name":"Shuting Cai","orcid":"https://orcid.org/0000-0002-2842-6439"},"institutions":[{"id":"https://openalex.org/I139024713","display_name":"Guangdong University of Technology","ror":"https://ror.org/04azbjn80","country_code":"CN","type":"education","lineage":["https://openalex.org/I139024713"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuting Cai","raw_affiliation_strings":["School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-2842-6439","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China","institution_ids":["https://openalex.org/I139024713"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100359310","display_name":"Weijun Li","orcid":"https://orcid.org/0000-0002-1227-0791"},"institutions":[{"id":"https://openalex.org/I139024713","display_name":"Guangdong University of Technology","ror":"https://ror.org/04azbjn80","country_code":"CN","type":"education","lineage":["https://openalex.org/I139024713"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weijun Li","raw_affiliation_strings":["School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-1227-0791","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China","institution_ids":["https://openalex.org/I139024713"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007822830","display_name":"Xiaoming Xiong","orcid":"https://orcid.org/0000-0002-2421-7621"},"institutions":[{"id":"https://openalex.org/I139024713","display_name":"Guangdong University of Technology","ror":"https://ror.org/04azbjn80","country_code":"CN","type":"education","lineage":["https://openalex.org/I139024713"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoming Xiong","raw_affiliation_strings":["School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-2421-7621","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China","institution_ids":["https://openalex.org/I139024713"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5978,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.82848986,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.901049017906189},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6947609186172485},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.651924192905426},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45153385400772095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3366376757621765}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.901049017906189},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6947609186172485},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.651924192905426},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45153385400772095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3366376757621765}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3728467","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3728467","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2912083425","https://openalex.org/W2991414967","https://openalex.org/W3033033241","https://openalex.org/W3085046840","https://openalex.org/W3141797743","https://openalex.org/W3169517138","https://openalex.org/W3210573375","https://openalex.org/W3215473801","https://openalex.org/W4211082391","https://openalex.org/W4226039771","https://openalex.org/W4286655084","https://openalex.org/W4297822279","https://openalex.org/W4360948889","https://openalex.org/W4362453037","https://openalex.org/W4366262984","https://openalex.org/W4368232696","https://openalex.org/W4376456993","https://openalex.org/W4386241738","https://openalex.org/W4387385733","https://openalex.org/W4394569836","https://openalex.org/W4401723483"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2111241003","https://openalex.org/W3146360095","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2184011203","https://openalex.org/W2570254841"],"abstract_inverted_index":{"In":[0,56,113],"FPGA":[1],"routing,":[2],"machine":[3],"learning-based":[4,52],"optimization":[5,54,118],"methods":[6],"have":[7],"achieved":[8],"improved":[9],"routing":[10,40,53,117],"solutions":[11],"by":[12],"integrating":[13],"traditional":[14],"heuristics":[15],"with":[16,28],"predictive":[17],"capabilities.":[18],"However,":[19],"these":[20,44],"approaches":[21],"mostly":[22],"relied":[23],"on":[24,129],"single-task":[25],"learning":[26,73,77,152],"models":[27,153],"black-box":[29],"nature":[30],"and":[31,37,66,160,171,176,184],"often":[32],"neglected":[33],"the":[34,57,61,89,93,114,121,130,134,164,169],"complex":[35,170],"trade-offs":[36],"inter-dependencies":[38],"between":[39,174],"metrics.":[41],"To":[42],"address":[43],"limitations,":[45],"this":[46,85],"paper":[47],"introduces":[48],"a":[49,71,109,190],"novel":[50],"multi-task":[51,72,76],"method.":[55],"congestion-wirelength":[58,90,110,115],"co-learning":[59],"stage,":[60,120],"simultaneous":[62],"prediction":[63,158],"of":[64,95,156],"congestion":[65,96,140,175],"wirelength":[67,98],"is":[68,81,99,126],"formulated":[69],"as":[70,106],"problem.":[74],"A":[75],"model,":[78],"named":[79],"CWNet,":[80],"proposed":[82],"to":[83,97,136,194],"tackle":[84],"challenge":[86],"effectively.":[87],"During":[88],"impact":[91,111,131,165],"interpretation,":[92],"contribution":[94],"quantified":[100],"using":[101],"an":[102],"XAI":[103],"technique":[104],"known":[105],"DeepSHAP,":[107],"producing":[108],"map.":[112],"co-guided":[116],"(CWRO)":[119],"VTR":[122],"router\u2019s":[123],"lookahead":[124],"map":[125,166],"enhanced":[127],"based":[128],"map,":[132],"guiding":[133],"router":[135],"avoid":[137],"locations":[138],"where":[139],"significantly":[141,180],"affect":[142],"wirelength.":[143,177],"Experimental":[144],"results":[145],"demonstrate":[146],"that":[147],"CWNet":[148],"outperforms":[149],"most":[150],"baseline":[151,195],"in":[154],"terms":[155],"both":[157],"performance":[159],"computational":[161],"efficiency.":[162],"Additionally,":[163],"visually":[167],"illustrates":[168],"nonlinear":[172],"relationship":[173],"Ultimately,":[178],"CWRO":[179],"reduces":[181],"congestion,":[182],"wirelength,":[183],"critical":[185],"path":[186],"delay,":[187],"while":[188],"maintaining":[189],"competitive":[191],"runtime":[192],"compared":[193],"routers.":[196]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-12T08:23:45.883708","created_date":"2025-10-10T00:00:00"}
