{"id":"https://openalex.org/W4410400499","doi":"https://doi.org/10.1145/3728179.3728182","title":"Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs","display_name":"Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs","publication_year":2025,"publication_date":"2025-05-15","ids":{"openalex":"https://openalex.org/W4410400499","doi":"https://doi.org/10.1145/3728179.3728182"},"language":"en","primary_location":{"id":"doi:10.1145/3728179.3728182","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3728179.3728182","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3728179.3728182","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115604914","display_name":"Xiaoke Wang","orcid":"https://orcid.org/0009-0003-8435-3478"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Xiaoke Wang","raw_affiliation_strings":["Department of Electronics and Information Systems, Ghent University, Ghent, Belgium"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Ghent University, Ghent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004502321","display_name":"Dirk Stroobandt","orcid":"https://orcid.org/0000-0002-4477-5313"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Dirk Stroobandt","raw_affiliation_strings":["Department of Electronics and Information Systems, Ghent University, Gent, Belgium"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Ghent University, Gent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5115604914"],"corresponding_institution_ids":["https://openalex.org/I32597200"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08872202,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"142","last_page":"146"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7625529170036316},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6903175115585327},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6029301881790161},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5613244771957397},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34075507521629333},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29370468854904175},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14426538348197937}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7625529170036316},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6903175115585327},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6029301881790161},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5613244771957397},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34075507521629333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29370468854904175},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14426538348197937}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3728179.3728182","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3728179.3728182","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:2503.06257","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2503.06257","pdf_url":"https://arxiv.org/pdf/2503.06257","source":{"id":"https://openalex.org/S4393918464","display_name":"ArXiv.org","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"pmh:oai:archive.ugent.be:01JVSEKN53QV9STPFSBWNYS81Z","is_oa":true,"landing_page_url":"http://hdl.handle.net/1854/LU-01JVSEKN53QV9STPFSBWNYS81Z","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9798400714320","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"doi:10.1145/3728179.3728182","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3728179.3728182","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3989317605","display_name":null,"funder_award_id":"202307650033","funder_id":"https://openalex.org/F4320322725","funder_display_name":"China Scholarship Council"}],"funders":[{"id":"https://openalex.org/F4320322725","display_name":"China Scholarship Council","ror":"https://ror.org/04atp4p48"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1970296212","https://openalex.org/W2005602803","https://openalex.org/W2020549672","https://openalex.org/W2029031086","https://openalex.org/W2033549713","https://openalex.org/W2039288205","https://openalex.org/W2111756578","https://openalex.org/W2139637699","https://openalex.org/W2144321909","https://openalex.org/W2155316178","https://openalex.org/W2161125053","https://openalex.org/W2713385151","https://openalex.org/W3033033241","https://openalex.org/W4318684489","https://openalex.org/W4384833499","https://openalex.org/W4389166655","https://openalex.org/W4399723230","https://openalex.org/W4406758898"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2111241003","https://openalex.org/W2390279801","https://openalex.org/W2014709025","https://openalex.org/W4391913857","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Packing":[0],"is":[1,93],"a":[2,20,35,50],"crucial":[3],"step":[4],"of":[5,53],"FPGA":[6,74,81],"design,":[7],"directly":[8,61],"impacting":[9],"interconnect":[10],"complexity,":[11],"routing":[12,97],"congestion,":[13],"and":[14,43,76,84,109],"overall":[15],"performance.":[16],"This":[17],"paper":[18],"presents":[19],"post-packing":[21,41],"interconnect-aware":[22,89],"analysis,":[23],"illustrating":[24],"how":[25,70],"dense":[26],"(sparse)":[27],"packing":[28,55,71,82],"changes":[29],"the":[30],"interconnection":[31],"structure.":[32],"We":[33],"introduce":[34],"new":[36],"metric,":[37],"RDensity,":[38],"to":[39,94],"define":[40],"density":[42,60],"investigate":[44],"its":[45],"influence":[46],"on":[47],"routability.":[48,63],"Through":[49],"comparative":[51],"study":[52],"two":[54],"tools,":[56],"we":[57],"demonstrate":[58],"that":[59],"impacts":[62],"Our":[64],"findings":[65],"provide":[66],"valuable":[67],"insights":[68],"into":[69],"decisions":[72],"affect":[73],"efficiency":[75],"offer":[77],"guidance":[78],"for":[79],"improving":[80],"tools":[83],"architecture":[85],"design":[86],"by":[87],"integrating":[88],"methods.":[90],"The":[91],"goal":[92],"achieve":[95],"efficient":[96],"while":[98],"maintaining":[99],"an":[100],"optimal":[101],"balance":[102],"between":[103],"cluster":[104],"density,":[105],"CLB":[106],"pin":[107],"counts,":[108],"logical":[110],"block":[111],"sizes.":[112]},"counts_by_year":[],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}