{"id":"https://openalex.org/W4412038587","doi":"https://doi.org/10.1145/3719276.3725172","title":"CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor","display_name":"CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor","publication_year":2025,"publication_date":"2025-05-28","ids":{"openalex":"https://openalex.org/W4412038587","doi":"https://doi.org/10.1145/3719276.3725172"},"language":"en","primary_location":{"id":"doi:10.1145/3719276.3725172","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3719276.3725172","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3719276.3725172","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5118825885","display_name":"Christopher Reinwardt","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Christopher Reinwardt","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"raw_orcid":"https://orcid.org/0009-0004-3184-0763","affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057338073","display_name":"Robert Balas","orcid":"https://orcid.org/0000-0002-7231-9315"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Robert Balas","raw_affiliation_strings":["ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-7231-9315","affiliations":[{"raw_affiliation_string":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017154351","display_name":"Alessandro Ottaviano","orcid":"https://orcid.org/0009-0000-9924-3536"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Alessandro Ottaviano","raw_affiliation_strings":["ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"raw_orcid":"https://orcid.org/0009-0000-9924-3536","affiliations":[{"raw_affiliation_string":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052915995","display_name":"Angelo Garofalo","orcid":"https://orcid.org/0000-0002-7495-6895"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Angelo Garofalo","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"raw_orcid":"https://orcid.org/0000-0002-7495-6895","affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["ETH Z\u00fcrich, Z\u00fcrich, Switzerland and University of Bologna, Bologna, Italy"],"raw_orcid":"https://orcid.org/0000-0001-8068-3806","affiliations":[{"raw_affiliation_string":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland and University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294","https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5118825885"],"corresponding_institution_ids":["https://openalex.org/I35440088"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1551671,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"116","last_page":"123"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7598046064376831},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.7300816774368286},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6369315385818481},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.6200459003448486},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.5192853808403015},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5133377909660339},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.42816686630249023},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38622957468032837},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3761042654514313},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3708786964416504},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37029901146888733},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3481978476047516},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34153062105178833},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14108461141586304},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13232719898223877}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7598046064376831},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.7300816774368286},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6369315385818481},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.6200459003448486},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.5192853808403015},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5133377909660339},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.42816686630249023},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38622957468032837},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3761042654514313},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3708786964416504},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37029901146888733},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3481978476047516},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34153062105178833},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14108461141586304},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13232719898223877},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3719276.3725172","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3719276.3725172","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/1025797","is_oa":false,"landing_page_url":"https://hdl.handle.net/11585/1025797","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"doi:10.1145/3719276.3725172","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3719276.3725172","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd ACM International Conference on Computing Frontiers","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1565155098","https://openalex.org/W1593242209","https://openalex.org/W1963479629","https://openalex.org/W2597954073","https://openalex.org/W2936567838","https://openalex.org/W3184118166","https://openalex.org/W4382119943"],"related_works":["https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W1976766385","https://openalex.org/W4310584696","https://openalex.org/W4237840813","https://openalex.org/W2128502296","https://openalex.org/W4385730960","https://openalex.org/W2993622674","https://openalex.org/W1833044483","https://openalex.org/W4364295250"],"abstract_inverted_index":{"The":[0],"increasing":[1],"complexity":[2],"of":[3,70,109,136,191],"autonomous":[4],"systems":[5],"has":[6],"driven":[7],"a":[8,160,203],"shift":[9],"to":[10,115,122,188,212],"integrated":[11],"heterogeneous":[12],"SoCs":[13],"with":[14,52,85,178,201],"real-time":[15],"and":[16,22,42,48,97,138,143,148,207],"safety":[17],"demands.":[18],"Ensuring":[19],"deterministic":[20],"WCETs":[21],"low-latency":[23],"for":[24,79,127,152,168],"critical":[25,128,153,169,193],"tasks":[26],"requires":[27],"minimizing":[28],"interference":[29,174],"on":[30,181],"shared":[31],"resources":[32],"like":[33],"virtual":[34,82],"memory.":[35],"Existing":[36],"techniques,":[37],"such":[38],"as":[39],"software":[40],"coloring":[41],"memory":[43,54,83,101,129],"replication,":[44],"introduce":[45],"significant":[46],"area":[47,87,205],"performance":[49],"overhead,":[50],"especially":[51],"virtualized":[53,161],"where":[55],"address":[56,62,125],"translation":[57,126],"adds":[58],"latency":[59],"uncertainty.":[60],"To":[61],"these":[63],"limitations,":[64],"we":[65],"propose":[66],"CVA6-VMRT,":[67],"an":[68],"extension":[69],"the":[71,112,192,213],"open-source":[72],"RISC-V":[73],"CVA6":[74,215],"core,":[75],"adding":[76],"hardware":[77],"support":[78],"predictability":[80],"in":[81],"access":[84,150],"minimal":[86,179],"overhead.":[88],"CVA6-VMRT":[89,132,163],"features":[90],"dynamically":[91],"partitioned":[92],"Translation":[93],"Look-aside":[94],"Buffers":[95],"(TLBs)":[96],"hybrid":[98],"L1":[99],"cache/scratchpad":[100],"(SPM)":[102],"functionality.":[103],"It":[104],"allows":[105],"fine-grained":[106],"per-thread":[107],"control":[108],"resources,":[110],"enabling":[111],"operating":[113],"system":[114],"manage":[116],"TLB":[117],"replacements,":[118],"including":[119],"static":[120],"overwrites,":[121],"ensure":[123],"single-cycle":[124],"regions.":[130],"Additionally,":[131],"enables":[133],"runtime":[134],"partitioning":[135],"data":[137,154],"instruction":[139],"caches":[140],"into":[141],"cache":[142],"SPM":[144],"sections,":[145],"providing":[146],"low":[147],"predictable":[149],"times":[151],"without":[155],"impacting":[156],"other":[157],"accesses.":[158],"In":[159],"setting,":[162],"enhances":[164],"execution":[165,185,190],"time":[166,186],"determinism":[167],"guests":[170,194],"by":[171],"94%":[172],"during":[173],"from":[175],"non-critical":[176],"guests,":[177],"impact":[180],"their":[182],"average":[183],"absolute":[184],"compared":[187,211],"isolated":[189],"only.":[195],"This":[196],"interference-aware":[197],"behaviour":[198],"is":[199],"achieved":[200],"just":[202],"4%":[204],"overhead":[206],"no":[208],"timing":[209],"penalty":[210],"baseline":[214],"core.":[216]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}