{"id":"https://openalex.org/W4406758898","doi":"https://doi.org/10.1145/3708358.3709350","title":"The Influence of Interconnection Complexity on the FPGA CAD Flow","display_name":"The Influence of Interconnection Complexity on the FPGA CAD Flow","publication_year":2024,"publication_date":"2024-10-31","ids":{"openalex":"https://openalex.org/W4406758898","doi":"https://doi.org/10.1145/3708358.3709350"},"language":"en","primary_location":{"id":"doi:10.1145/3708358.3709350","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3708358.3709350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115604914","display_name":"Xiaoke Wang","orcid":"https://orcid.org/0009-0003-8435-3478"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Xiaoke Wang","raw_affiliation_strings":["Department of Electronics and Information Systems, Hardware and Embedded Systems Group, Ghent University, Ghent, Belgium"],"raw_orcid":"https://orcid.org/0009-0003-8435-3478","affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Hardware and Embedded Systems Group, Ghent University, Ghent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004502321","display_name":"Dirk Stroobandt","orcid":"https://orcid.org/0000-0002-4477-5313"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Dirk Stroobandt","raw_affiliation_strings":["Department of Electronics and Information Systems, Hardware and Embedded Systems Group, Ghent University, Ghent, Belgium"],"raw_orcid":"https://orcid.org/0000-0002-4477-5313","affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Hardware and Embedded Systems Group, Ghent University, Ghent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3712,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62655578,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7451415061950684},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7407013177871704},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7011054754257202},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.6937909126281738},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.5130240321159363},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48215076327323914},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.431831955909729},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3702280819416046},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.345978319644928},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.16654551029205322},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15064680576324463},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.12160331010818481},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07759737968444824}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7451415061950684},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7407013177871704},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7011054754257202},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.6937909126281738},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.5130240321159363},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48215076327323914},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.431831955909729},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3702280819416046},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.345978319644928},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.16654551029205322},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15064680576324463},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.12160331010818481},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07759737968444824},{"id":"https://openalex.org/C57879066","wikidata":"https://www.wikidata.org/wiki/Q41217","display_name":"Mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3708358.3709350","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3708358.3709350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding","raw_type":"proceedings-article"},{"id":"pmh:oai:archive.ugent.be:01JJCETBDTH8VMVJ6XXH8WH8AX","is_oa":false,"landing_page_url":"https://biblio.ugent.be/publication/01JJCETBDTH8VMVJ6XXH8WH8AX","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:archive.ugent.be:01JJCESCQJ44MSVS75HPQJHDNQ","is_oa":false,"landing_page_url":"http://hdl.handle.net/1854/LU-01JJCESCQJ44MSVS75HPQJHDNQ","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9798400714009","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7465873043","display_name":null,"funder_award_id":"202307650033","funder_id":"https://openalex.org/F4320323817","funder_display_name":"Universitas Brawijaya"}],"funders":[{"id":"https://openalex.org/F4320323817","display_name":"Universitas Brawijaya","ror":"https://ror.org/01wk3d929"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1590243758","https://openalex.org/W1970296212","https://openalex.org/W2008694370","https://openalex.org/W2048582679","https://openalex.org/W2055251702","https://openalex.org/W2093850329","https://openalex.org/W2121263056","https://openalex.org/W2134401041","https://openalex.org/W2139637699","https://openalex.org/W2161125053","https://openalex.org/W2164340799","https://openalex.org/W3028955404","https://openalex.org/W3033033241","https://openalex.org/W4368232696","https://openalex.org/W4391857786","https://openalex.org/W4399723230"],"related_works":["https://openalex.org/W2091330445","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2138022277","https://openalex.org/W1631753024","https://openalex.org/W2004325343","https://openalex.org/W2533212402","https://openalex.org/W2592133661","https://openalex.org/W2121865749"],"abstract_inverted_index":{"Moore's":[0],"Law":[1],"has":[2],"been":[3],"guiding":[4],"the":[5,8,12],"development":[6],"of":[7],"VLSI":[9,45],"industry":[10],"for":[11,40],"past":[13],"half-century.":[14],"This":[15],"law":[16],"underscores":[17],"fabrication":[18],"technology's":[19],"crucial":[20],"role":[21],"in":[22,44],"enhancing":[23],"chip":[24],"performance.":[25],"However,":[26],"with":[27],"technology":[28],"nearing":[29],"physical":[30],"limitations,":[31],"we":[32],"envisage":[33],"that":[34],"there":[35],"is":[36],"still":[37],"significant":[38],"potential":[39],"optimizing":[41],"interconnection":[42],"complexity":[43],"design.":[46]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
