{"id":"https://openalex.org/W4407953462","doi":"https://doi.org/10.1145/3706628.3708880","title":"FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis","display_name":"FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis","publication_year":2025,"publication_date":"2025-02-26","ids":{"openalex":"https://openalex.org/W4407953462","doi":"https://doi.org/10.1145/3706628.3708880"},"language":"en","primary_location":{"id":"doi:10.1145/3706628.3708880","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3706628.3708880","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1145/3706628.3708880","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065008474","display_name":"Louis Coulon","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Louis Coulon","raw_affiliation_strings":["School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0009-0002-4605-4955","affiliations":[{"raw_affiliation_string":"School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Lucas Ramirez","orcid":"https://orcid.org/0009-0008-5656-4047"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Lucas Ramirez","raw_affiliation_strings":["School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0009-0008-5656-4047","affiliations":[{"raw_affiliation_string":"School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102812429","display_name":"Jason H. Anderson","orcid":"https://orcid.org/0000-0001-9083-6853"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jason Anderson","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Toronto, Toronto, Canada"],"raw_orcid":"https://orcid.org/0000-0001-9083-6853","affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045601003","display_name":"Mirjana Stojilovi\u0107","orcid":"https://orcid.org/0000-0001-5649-5020"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Mirjana Stojilovi\u0107","raw_affiliation_strings":["School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-5649-5020","affiliations":[{"raw_affiliation_string":"School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020575991","display_name":"Paolo Ienne","orcid":"https://orcid.org/0000-0002-6142-7345"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Paolo Ienne","raw_affiliation_strings":["School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-6142-7345","affiliations":[{"raw_affiliation_string":"School of Computer and Communication Sciences, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.0667,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.96187856,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"147","last_page":"158"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6784838438034058},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4704156219959259},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3606148362159729},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3401043117046356}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6784838438034058},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4704156219959259},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3606148362159729},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3401043117046356}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3706628.3708880","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3706628.3708880","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3706628.3708880","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3706628.3708880","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W1977850862","https://openalex.org/W2018055497","https://openalex.org/W2030765577","https://openalex.org/W2047143252","https://openalex.org/W2050973642","https://openalex.org/W2097683623","https://openalex.org/W2104869032","https://openalex.org/W2140956115","https://openalex.org/W2147088458","https://openalex.org/W2147405597","https://openalex.org/W2626186664","https://openalex.org/W2626211758","https://openalex.org/W2741661236","https://openalex.org/W2790678706","https://openalex.org/W2912425543","https://openalex.org/W2980270412","https://openalex.org/W3008412028","https://openalex.org/W3016769527","https://openalex.org/W3033033241","https://openalex.org/W3093982621","https://openalex.org/W3159763498","https://openalex.org/W3164157068","https://openalex.org/W3166559827","https://openalex.org/W3190681843","https://openalex.org/W3191007950","https://openalex.org/W4213347724","https://openalex.org/W4236272793","https://openalex.org/W4241238426","https://openalex.org/W4250523893","https://openalex.org/W4293025825","https://openalex.org/W4308084052","https://openalex.org/W4312942943","https://openalex.org/W4321637175","https://openalex.org/W4321637234","https://openalex.org/W4321637475","https://openalex.org/W4383604851","https://openalex.org/W4384833496","https://openalex.org/W4385080008","https://openalex.org/W4385585403","https://openalex.org/W4401017906","https://openalex.org/W4404133172"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"Reconfigurable":[0],"computing":[1],"fabrics":[2],"include":[3],"FPGAs":[4,7],"and":[5,12,28,112,133],"CGRAs.":[6],"offer":[8],"flexible":[9],"bit-level":[10],"reconfigurability":[11],"can":[13],"map":[14],"almost":[15],"any":[16],"program":[17],"via":[18],"high-level":[19],"synthesis":[20],"(HLS)":[21],"compilers,":[22],"but":[23,40,150],"they":[24,94],"incur":[25],"high":[26,118],"area":[27,155],"speed":[29,148],"overheads":[30],"compared":[31,157],"to":[32,98,129,158],"ASICs.":[33],"CGRAs,":[34],"in":[35],"contrast,":[36],"provide":[37],"ASIC-like":[38],"performance":[39],"limited":[41],"flexibility,":[42],"typically":[43],"supporting":[44],"only":[45,152],"feedforward":[46],"programs":[47],"with":[48,121],"unambiguous":[49],"memory":[50],"accesses,":[51],"far":[52],"from":[53],"the":[54,88,163],"capabilities":[55],"of":[56,65,101,146],"HLS":[57,73],"compilers.":[58],"This":[59],"work":[60],"introduces":[61],"a":[62,99,127,135,153],"new":[63],"class":[64],"reconfigurable":[66],"arrays":[67,105,132],"inspired":[68],"by":[69],"modern":[70],"dynamically":[71],"scheduled":[72],"(DHLS)":[74],"tools.":[75],"Unlike":[76],"traditional":[77],"HLS,":[78],"DHLS":[79,139],"compilers":[80],"no":[81],"longer":[82],"produce":[83],"explicit":[84],"state":[85],"machines,":[86],"eliminating":[87],"need":[89],"for":[90,117],"look-up":[91],"tables.":[92],"Instead,":[93],"delegate":[95],"scheduling":[96],"decisions":[97],"set":[100],"coarse-grained":[102],"primitives.":[103],"Our":[104],"leverage":[106],"these":[107,131],"primitives":[108],"as":[109],"processing":[110],"elements":[111],"combine":[113],"FPGA-style":[114],"interconnect":[115],"topology":[116],"routing":[119],"flexibility":[120],"CGRA-like":[122],"bus-based":[123],"interconnect.":[124],"We":[125],"present":[126],"framework":[128],"explore":[130],"evaluate":[134],"preliminary":[136],"architecture":[137],"using":[138],"benchmarks.":[140],"The":[141],"results":[142],"show":[143],"an":[144,159],"average":[145],"~2\u00d7":[147],"improvement,":[149],"unfortunately":[151],"~20%":[154],"reduction":[156],"FPGA":[160],"implemented":[161],"on":[162],"same":[164],"technology":[165],"node.":[166]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":2}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}
