{"id":"https://openalex.org/W4407953460","doi":"https://doi.org/10.1145/3706628.3708838","title":"Measuring the Minimum Power Requirement of FPGA Architectural Specifications","display_name":"Measuring the Minimum Power Requirement of FPGA Architectural Specifications","publication_year":2025,"publication_date":"2025-02-26","ids":{"openalex":"https://openalex.org/W4407953460","doi":"https://doi.org/10.1145/3706628.3708838"},"language":"en","primary_location":{"id":"doi:10.1145/3706628.3708838","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3706628.3708838","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068830776","display_name":"Andy Ye","orcid":"https://orcid.org/0000-0002-2959-5736"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andy Ye","raw_affiliation_strings":["Department of Electrical, Computer, and Biomedical Engineering, Toronto Metropolitan University, Toronto, Ontario, Canada"],"raw_orcid":"https://orcid.org/0000-0002-2959-5736","affiliations":[{"raw_affiliation_string":"Department of Electrical, Computer, and Biomedical Engineering, Toronto Metropolitan University, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076896575","display_name":"Anas Razzaq","orcid":"https://orcid.org/0000-0002-7708-9299"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Anas Razzaq","raw_affiliation_strings":["Department of Electrical, Computer, and Biomedical Engineering, Toronto Metropolitan University, Toronto, Ontario, Canada"],"raw_orcid":"https://orcid.org/0000-0002-7708-9299","affiliations":[{"raw_affiliation_string":"Department of Electrical, Computer, and Biomedical Engineering, Toronto Metropolitan University, Toronto, Ontario, Canada","institution_ids":["https://openalex.org/I530967"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I530967"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"180","last_page":"180"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6180715560913086},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.578596293926239},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.48181548714637756},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4321986734867096},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4136182367801666},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4017593264579773},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.262763112783432}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6180715560913086},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.578596293926239},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.48181548714637756},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4321986734867096},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4136182367801666},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4017593264579773},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.262763112783432},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3706628.3708838","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3706628.3708838","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Bypass":[0],"capacitances":[1,29,40,59,79,106,278],"bridge":[2],"the":[3,16,38,62,73,76,86,100,103,116,126,142,146,157,162,173,194,210,218,280],"gap":[4],"between":[5],"momentary":[6],"surges":[7],"of":[8,18,41,65,75,102,118,141,156,196,214,222,240,258,283],"power":[9,19,95,114,147,159,174,220,281,297],"demand":[10],"caused":[11],"by":[12,90,161,167],"switching":[13],"transistors":[14,43],"and":[15,188,217,279],"ability":[17,74,101],"supplies":[20],"to":[21,23,71,134,139,152,236,255,290],"respond":[22],"these":[24],"surges.":[25],"Even":[26],"though":[27],"bypass":[28,52,58,78,105,277],"are":[30],"not":[31],"explicitly":[32],"specified":[33],"in":[34,44,80,107,115,131,184,229,232,251,288],"FPGA":[35,46,87,119,272,293],"architectural":[36,120,273],"specifications,":[37],"gate":[39],"quiescent":[42,77,104],"an":[45,66,168],"architecture":[47],"can":[48,60],"act":[49],"as":[50],"symbiotic":[51],"capacitances.":[53],"Since":[54],"any":[55],"additional":[56],"dedicated":[57],"increase":[61],"implementation":[63],"area":[64],"FPGA,":[67],"it":[68],"is":[69,88,176],"important":[70],"measure":[72],"maintaining":[81,108],"stable":[82,109],"operating":[83],"voltages":[84,111],"while":[85,243],"powered":[89,166],"voltage":[91,170,284],"sources":[92,285],"with":[93,261],"limited":[94,113],"outputs.":[96],"This":[97],"work":[98],"measures":[99],"supply":[110],"under":[112],"context":[117],"investigations.":[121],"We":[122],"found":[123],"that,":[124],"for":[125,295],"12-LUT":[127],"logic":[128,164],"cluster":[129,165],"investigated":[130],"this":[132],"work,":[133],"limit":[135,282],"VDD":[136,144,179,205,212,233,252],"value":[137,180,213,234,239,253],"droop":[138,181],"5%":[140],"nominal":[143,211],"value,":[145],"source":[148],"must":[149],"be":[150],"able":[151],"produce":[153],"3":[154],"times":[155],"average":[158],"consumed":[160],"same":[163],"ideal":[169],"source.":[171],"When":[172],"output":[175,221],"further":[177],"reduced,":[178],"increases,":[182],"resulting":[183],"significantly":[185],"increased":[186],"delay":[187],"reduced":[189],"noise":[190],"margin.":[191],"In":[192,207],"addition,":[193],"degree":[195],"parallel":[197,230],"execution":[198],"also":[199],"has":[200],"a":[201,237,248,256],"significant":[202],"effect":[203],"on":[204],"value.":[206],"particular,":[208],"at":[209,247],"0.9":[215],"volts":[216,242],"maximum":[219],"28.1":[223],"uW,":[224],"executing":[225,244],"all":[226],"12":[227],"LUTs":[228],"results":[231,250,269],"drooping":[235,254],"minimum":[238,257],"0.370":[241],"1":[245],"LUT":[246],"time":[249],"0.690":[259],"volts,":[260],"both":[262],"cases":[263],"achieving":[264],"similar":[265],"computing":[266],"time.":[267],"These":[268],"suggest":[270],"that":[271],"evaluations":[274],"should":[275],"take":[276],"into":[286],"consideration":[287],"order":[289],"design":[291],"efficient":[292],"architectures":[294],"low":[296],"applications.":[298]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}