{"id":"https://openalex.org/W4407953393","doi":"https://doi.org/10.1145/3706628.3708824","title":"TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms","display_name":"TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms","publication_year":2025,"publication_date":"2025-02-26","ids":{"openalex":"https://openalex.org/W4407953393","doi":"https://doi.org/10.1145/3706628.3708824"},"language":"en","primary_location":{"id":"doi:10.1145/3706628.3708824","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3706628.3708824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009437726","display_name":"Enlai Li","orcid":"https://orcid.org/0000-0001-8486-3695"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Enlai Li","raw_affiliation_strings":["Hong Kong University of Science and Technology, Kowloon, Hong Kong"],"raw_orcid":"https://orcid.org/0000-0001-8486-3695","affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology, Kowloon, Hong Kong","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101564905","display_name":"Zhe Lin","orcid":"https://orcid.org/0009-0002-1594-2335"},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhe Lin","raw_affiliation_strings":["Sun Yat-Sen University, Shenzhen, Guangdong, China"],"raw_orcid":"https://orcid.org/0009-0002-1594-2335","affiliations":[{"raw_affiliation_string":"Sun Yat-Sen University, Shenzhen, Guangdong, China","institution_ids":["https://openalex.org/I157773358"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024130730","display_name":"Sharad Sinha","orcid":"https://orcid.org/0000-0002-4532-2017"},"institutions":[{"id":"https://openalex.org/I4210112052","display_name":"Indian Institute of Technology Goa","ror":"https://ror.org/02v7trd43","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210112052"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sharad Sinha","raw_affiliation_strings":["Indian Institute of Technology Goa, Goa, India"],"raw_orcid":"https://orcid.org/0000-0002-4532-2017","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Goa, Goa, India","institution_ids":["https://openalex.org/I4210112052"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061515087","display_name":"Wei Zhang","orcid":"https://orcid.org/0000-0002-7622-6714"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["Hong Kong University of Science and Technology, Kowloon, Hong Kong"],"raw_orcid":"https://orcid.org/0000-0002-7622-6714","affiliations":[{"raw_affiliation_string":"Hong Kong University of Science and Technology, Kowloon, Hong Kong","institution_ids":["https://openalex.org/I200769079"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01700613,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"85","last_page":"91"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7923232316970825},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6258981823921204},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5796776413917542},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5552173852920532},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5382236242294312},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4438113570213318},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.44152766466140747},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4261837601661682},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42102450132369995},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36682429909706116},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.05929684638977051}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7923232316970825},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6258981823921204},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5796776413917542},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5552173852920532},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5382236242294312},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4438113570213318},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.44152766466140747},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4261837601661682},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42102450132369995},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36682429909706116},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.05929684638977051},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3706628.3708824","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3706628.3708824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-148205","is_oa":false,"landing_page_url":"http://repository.hkust.edu.hk/ir/Record/1783.1-148205","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2642413362","display_name":null,"funder_award_id":"2023YFB4405100","funder_id":"https://openalex.org/F4320323817","funder_display_name":"Universitas Brawijaya"}],"funders":[{"id":"https://openalex.org/F4320323817","display_name":"Universitas Brawijaya","ror":"https://ror.org/01wk3d929"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2145023843","https://openalex.org/W2263733277","https://openalex.org/W2291075189","https://openalex.org/W2625058759","https://openalex.org/W2769934311","https://openalex.org/W2895222162","https://openalex.org/W2911433361","https://openalex.org/W2917675277","https://openalex.org/W2927326457","https://openalex.org/W4229673714","https://openalex.org/W4230571165","https://openalex.org/W4293213271","https://openalex.org/W4320063558","https://openalex.org/W4392207843"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2133682266","https://openalex.org/W2497617944","https://openalex.org/W2167303720","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966","https://openalex.org/W3147501184"],"abstract_inverted_index":{"CPU-FPGA":[0,15,40],"SoC":[1],"architectures":[2,38,140],"with":[3,114,133],"multiple":[4],"shared":[5],"coherent":[6,36,66],"caches":[7],"reduce":[8],"inter-component":[9],"communication":[10,45,121],"overhead":[11,46],"and":[12,29,33,69,119,123,138],"enable":[13],"efficient":[14,84],"collaboration":[16],"through":[17],"task":[18,61],"partitioning.":[19],"However,":[20],"existing":[21],"studies":[22],"primarily":[23],"focus":[24],"on":[25,39,107],"optimizing":[26],"partitioning":[27,50,62,75,95,127,131,142],"units":[28,96],"ignore":[30],"the":[31,48],"benefits":[32],"diversity":[34],"of":[35,136],"cache":[37,67,108],"SoCs,":[41],"leading":[42],"to":[43,78,93,110,129],"extra":[44],"in":[47],"final":[49],"decisions.":[51],"To":[52],"address":[53],"this,":[54],"we":[55],"propose":[56],"TAPCA,":[57],"a":[58,88,101,124],"memory":[59,102,117,139],"interface-aware":[60],"framework":[63],"that":[64],"integrates":[65],"management":[68,103],"selection.":[70],"TAPCA":[71],"includes":[72],"an":[73],"adaptive":[74],"unit":[76,113],"generator":[77],"identify":[79],"essential":[80],"application":[81],"structures":[82],"for":[83,141],"design":[85,89,99],"space":[86,90],"exploration,":[87],"exploration":[91],"module":[92,105],"profile":[94],"across":[97],"various":[98],"points,":[100],"modeling":[104],"based":[106],"bypassing":[109],"match":[111],"each":[112],"its":[115],"optimal":[116],"architecture":[118],"assess":[120],"overhead,":[122],"knapsack":[125],"problem":[126],"solver":[128],"determine":[130],"decisions":[132],"appropriate":[134],"configurations":[135],"hardware":[137],"units.":[143]},"counts_by_year":[],"updated_date":"2026-08-18T07:49:30.821534","created_date":"2025-10-10T00:00:00"}