{"id":"https://openalex.org/W4402526467","doi":"https://doi.org/10.1145/3679007.3685064","title":"mruby on Resource-Constrained Low-Power Coprocessors of Embedded Devices","display_name":"mruby on Resource-Constrained Low-Power Coprocessors of Embedded Devices","publication_year":2024,"publication_date":"2024-09-13","ids":{"openalex":"https://openalex.org/W4402526467","doi":"https://doi.org/10.1145/3679007.3685064"},"language":"en","primary_location":{"id":"doi:10.1145/3679007.3685064","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3679007.3685064","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3679007.3685064?download=true","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3679007.3685064?download=true","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055408127","display_name":"Go Suzuki","orcid":"https://orcid.org/0009-0008-1927-4825"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Go Suzuki","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0009-0008-1927-4825","affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074965608","display_name":"Takuo Watanabe","orcid":"https://orcid.org/0000-0001-7470-3428"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takuo Watanabe","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0001-7470-3428","affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005203197","display_name":"Sosuke Moriguchi","orcid":"https://orcid.org/0000-0002-4153-4514"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Sosuke Moriguchi","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0002-4153-4514","affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5055408127"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":1.8974,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.87031736,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"41","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.8730247020721436},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6099051833152771},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47195473313331604},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.4599721431732178},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4307517409324646},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32001787424087524},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08718517422676086}],"concepts":[{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.8730247020721436},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6099051833152771},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47195473313331604},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.4599721431732178},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4307517409324646},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32001787424087524},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08718517422676086},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3679007.3685064","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3679007.3685064","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3679007.3685064?download=true","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3679007.3685064","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3679007.3685064","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3679007.3685064?download=true","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4402526467.pdf","grobid_xml":"https://content.openalex.org/works/W4402526467.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W1515766771","https://openalex.org/W2028069406","https://openalex.org/W2121134342","https://openalex.org/W2130262734","https://openalex.org/W2964084063","https://openalex.org/W2971395071","https://openalex.org/W3206490075","https://openalex.org/W3209102573","https://openalex.org/W4382050657","https://openalex.org/W4387773876","https://openalex.org/W4391983995"],"related_works":["https://openalex.org/W2137567370","https://openalex.org/W2005724428","https://openalex.org/W2987062793","https://openalex.org/W2141458065","https://openalex.org/W2154961667","https://openalex.org/W2169599552","https://openalex.org/W2583923580","https://openalex.org/W4401155055","https://openalex.org/W2165099691","https://openalex.org/W2099064976"],"abstract_inverted_index":{"As":[0],"IoT":[1,84],"devices":[2],"advance,":[3],"their":[4],"microcontroller":[5],"systems-on-a-chip":[6],"(SoCs)":[7],"demand":[8],"higher":[9],"speeds,":[10],"more":[11],"memory,":[12],"and":[13,39,46,75,95,102,110,114],"advanced":[14],"peripherals,":[15],"leading":[16],"to":[17,38,59],"increased":[18],"power":[19,29,108],"consumption.":[20],"Integrating":[21],"low-power":[22],"(LP)":[23],"coprocessors":[24,42],"in":[25],"SoCs":[26],"can":[27],"reduce":[28],"usage":[30],"while":[31],"maintaining":[32],"responsiveness.":[33],"However,":[34],"switching":[35],"application":[36],"execution":[37],"from":[40],"the":[41,67,93,98],"generally":[43],"involves":[44],"complex":[45],"platform-specific":[47],"procedures.":[48],"We":[49],"propose":[50],"a":[51,72,76],"JIT":[52,73],"compilation":[53],"method":[54],"for":[55,66],"managed":[56],"programming":[57,68],"languages":[58],"streamline":[60],"LP":[61,87],"coprocessor":[62],"use.":[63],"Our":[64],"prototype":[65],"language":[69],"mruby":[70,100],"includes":[71],"compiler":[74],"seamless":[77],"processor-switching":[78],"mechanism,":[79],"enabling":[80],"rapid":[81],"development":[82],"of":[83,97,106],"applications":[85],"leveraging":[86],"coprocessors.":[88],"This":[89],"work-in-progress":[90],"paper":[91],"describes":[92],"design":[94],"implementation":[96],"extended":[99],"interpreter":[101],"presents":[103],"preliminary":[104],"evaluations":[105],"its":[107],"consumption":[109],"latency":[111],"on":[112],"ESP32-S3":[113],"ESP32-C6.":[115]},"counts_by_year":[{"year":2025,"cited_by_count":4}],"updated_date":"2026-03-13T14:20:09.374765","created_date":"2025-10-10T00:00:00"}
