{"id":"https://openalex.org/W4399677071","doi":"https://doi.org/10.1145/3673653","title":"Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture","display_name":"Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture","publication_year":2024,"publication_date":"2024-06-14","ids":{"openalex":"https://openalex.org/W4399677071","doi":"https://doi.org/10.1145/3673653"},"language":"en","primary_location":{"id":"doi:10.1145/3673653","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3673653","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3673653","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3673653","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056716458","display_name":"Ataberk Olgun","orcid":"https://orcid.org/0000-0001-5333-5726"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Ataberk Olgun","raw_affiliation_strings":["ETH Zurich, Zurich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-5333-5726","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012402623","display_name":"F. Nisa Bostanc\u0131","orcid":"https://orcid.org/0000-0002-2718-0297"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"F. Nisa Bostanci","raw_affiliation_strings":["ETH Zurich, Zurich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-2718-0297","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091016237","display_name":"Geraldo F. Oliveira","orcid":"https://orcid.org/0000-0003-1557-4819"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Geraldo Francisco de Oliveira Junior","raw_affiliation_strings":["ETH Zurich, Zurich Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-1557-4819","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090229323","display_name":"Yahya Can Tu\u011frul","orcid":"https://orcid.org/0009-0002-9291-3626"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Yahya Can Tugrul","raw_affiliation_strings":["ETH Zurich, Zurich Switzerland"],"raw_orcid":"https://orcid.org/0009-0002-9291-3626","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083434792","display_name":"Rahul Bera","orcid":"https://orcid.org/0000-0003-1129-1889"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Rahul Bera","raw_affiliation_strings":["ETH Zurich, Zurich Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-1129-1889","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001715701","display_name":"A. Giray Ya\u011fl\u0131k\u00e7\u0131","orcid":"https://orcid.org/0000-0002-9333-6077"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Abdullah Giray Yaglikci","raw_affiliation_strings":["ETH Zurich, Zurich Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-9333-6077","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032313427","display_name":"Hasan Hassan","orcid":"https://orcid.org/0000-0001-9766-007X"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Hasan Hassan","raw_affiliation_strings":["ETH Zurich, Zurich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-9766-007X","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052707216","display_name":"O\u011fuz Ergin","orcid":"https://orcid.org/0000-0003-2701-3787"},"institutions":[{"id":"https://openalex.org/I13236232","display_name":"TOBB University of Economics and Technology","ror":"https://ror.org/03ewx7v96","country_code":"TR","type":"education","lineage":["https://openalex.org/I13236232"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"Oguz Ergin","raw_affiliation_strings":["TOBB University of Economics and Technology, Ankara Turkey"],"raw_orcid":"https://orcid.org/0000-0003-2701-3787","affiliations":[{"raw_affiliation_string":"TOBB University of Economics and Technology, Ankara Turkey","institution_ids":["https://openalex.org/I13236232"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050695684","display_name":"Onur Mutlu","orcid":"https://orcid.org/0000-0002-0075-2312"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Onur Mutlu","raw_affiliation_strings":["ETH Zurich, Zurich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-0075-2312","affiliations":[{"raw_affiliation_string":"ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5056716458"],"corresponding_institution_ids":["https://openalex.org/I35440088"],"apc_list":null,"apc_paid":null,"fwci":4.0975,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.95227442,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"21","issue":"3","first_page":"1","last_page":"29"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8648226857185364},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.808303713798523},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6700266003608704},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5820461511611938},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5558444857597351},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5047398805618286},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.48884862661361694},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4859829843044281},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40578028559684753},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3243798017501831},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.15624916553497314},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.09044754505157471},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.08703139424324036}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8648226857185364},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.808303713798523},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6700266003608704},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5820461511611938},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5558444857597351},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5047398805618286},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.48884862661361694},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4859829843044281},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40578028559684753},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3243798017501831},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.15624916553497314},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.09044754505157471},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.08703139424324036}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3673653","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3673653","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3673653","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/3673653","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3673653","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3673653","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4399677071.pdf"},"referenced_works_count":21,"referenced_works":["https://openalex.org/W2012932717","https://openalex.org/W2023834387","https://openalex.org/W2025106479","https://openalex.org/W2027829345","https://openalex.org/W2034861439","https://openalex.org/W2040609657","https://openalex.org/W2054882590","https://openalex.org/W2058693334","https://openalex.org/W2067354926","https://openalex.org/W2092406519","https://openalex.org/W2110860124","https://openalex.org/W2112833506","https://openalex.org/W2116506644","https://openalex.org/W2129381159","https://openalex.org/W2151345470","https://openalex.org/W2156403661","https://openalex.org/W2518205541","https://openalex.org/W2725159389","https://openalex.org/W2916411819","https://openalex.org/W3129132785","https://openalex.org/W3196818429"],"related_works":["https://openalex.org/W4293430534","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2122646225","https://openalex.org/W3140615508","https://openalex.org/W4291214134","https://openalex.org/W2912837441","https://openalex.org/W2029945810","https://openalex.org/W1954780666"],"abstract_inverted_index":{"Modern":[0],"computing":[1,51],"systems":[2],"access":[3,18,56,205],"data":[4,66,96,106,167],"in":[5,122,135,149],"main":[6],"memory":[7,72,160,214,249,382],"at":[8,12,392],"coarse":[9],"granularity":[10],"(e.g.,":[11,34],"512-bit":[13],"cache":[14,46,116,137,146,150],"block":[15,138],"granularity).":[16],"Coarse-grained":[17],"leads":[19],"to":[20,59,126,216,234,254,265,287,306,376],"wasted":[21,60,90],"energy":[22,91,245,273,283,316,344],"because":[23],"the":[24,71,112,133,145,155,159,165,171,183,213,243,298,336],"system":[25,236,278],"does":[26,318],"not":[27,119,319],"use":[28],"all":[29],"individually":[30],"accessed":[31,143],"small":[32],"portions":[33,191],"words":[35,134,157,185],",":[36],"each":[37,204],"of":[38,44,179,192,201,247,285,297,300,335],"which":[39],"typically":[40],"is":[41,295,363],"64":[42],"bits)":[43],"a":[45,83,136,176,198,235,301,355],"block.":[47],"In":[48],"modern":[49,302],"DRAM-based":[50],"systems,":[52],"two":[53],"key":[54],"coarse-grained":[55,238],"mechanisms":[57],"lead":[58],"energy:":[61],"large":[62],"and":[63,70,74,98,151,173,211,323,346,366,372,380],"fixed-size":[64],"(i)":[65,152],"transfers":[67,153],"between":[68],"DRAM":[69,76,86,95,99,110,131,166,193,207,218,224,241,244,272,291,309,312,315,321,332,343,351,359,391],"controller":[73,215],"(ii)":[75,174],"row":[77,100],"activations.":[78],"We":[79,221],"propose":[80],"Sectored":[81,109,130,223,240,270,289,311,331,369,390],"DRAM,":[82,108,239],"new,":[84],"low-overhead":[85],"substrate":[87],"that":[88,114,139,181,368],"reduces":[89,242,314],"by":[92,162,186,252,263],"enabling":[93],"fine-grained":[94,308,358],"transfer":[97,168],"activation.":[101],"To":[102,384],"retrieve":[103],"only":[104,154],"useful":[105],"from":[107,228],"exploits":[111],"observation":[113],"many":[115,123],"blocks":[117],"are":[118],"fully":[120],"utilized":[121],"workloads":[124,227,251],"due":[125],"poor":[127],"spatial":[128],"locality.":[129],"predicts":[132],"will":[140,374],"likely":[141],"be":[142,325],"during":[144],"block\u2019s":[147],"residency":[148],"predicted":[156,184],"on":[158,203],"channel":[161],"dynamically":[163],"tailoring":[164],"size":[169],"for":[170],"workload":[172],"activates":[175],"smaller":[177,199],"set":[178,200],"cells":[180,202],"contain":[182],"carefully":[187],"operating":[188],"physically":[189],"isolated":[190],"rows":[194],"(i.e.,":[195],"mats).":[196],"Activating":[197],"relaxes":[206],"power":[208],"delivery":[209],"constraints":[210],"allows":[212,281],"schedule":[217],"accesses":[219],"faster.":[220],"evaluate":[222],"using":[225],"41":[226],"widely":[229],"used":[230],"benchmark":[231],"suites.":[232],"Compared":[233,305],"with":[237,276,327],"consumption":[246],"highly":[248],"intensive":[250],"up":[253,264,286,348],"(on":[255,266],"average)":[256,267],"33%":[257],"(20%)":[258],"while":[259],"improving":[260],"their":[261],"performance":[262,279,337],"36%":[268],"(17%).":[269],"DRAM\u2019s":[271,290,370],"savings,":[274],"combined":[275],"its":[277],"improvement,":[280],"system-wide":[282],"savings":[284],"23%.":[288],"chip":[292,352],"area":[293,299,353],"overhead":[294],"1.7%":[296],"DDR4":[303],"chip.":[304],"state-of-the-art":[307,357],"architectures,":[310],"greatly":[313],"consumption,":[317],"reduce":[320],"bandwidth,":[322],"can":[324],"implemented":[326],"low":[328],"hardware":[329],"cost.":[330],"provides":[333],"89%":[334],"benefits":[338],"of,":[339],"consumes":[340],"12%":[341],"less":[342,350],"than,":[345],"takes":[347],"34%":[349],"than":[354],"high-performance":[356,381],"architecture":[360],"(Half-DRAM).":[361],"It":[362],"our":[364],"hope":[365],"belief":[367],"ideas":[371],"results":[373],"help":[375],"enable":[377],"more":[378],"efficient":[379],"systems.":[383],"this":[385],"end,":[386],"we":[387],"open":[388],"source":[389],"https://github.com/CMU-SAFARI/Sectored-DRAM.":[393]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":2}],"updated_date":"2026-05-28T09:10:13.091523","created_date":"2025-10-10T00:00:00"}