{"id":"https://openalex.org/W4399723175","doi":"https://doi.org/10.1145/3665283.3665296","title":"Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures","display_name":"Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures","publication_year":2024,"publication_date":"2024-06-17","ids":{"openalex":"https://openalex.org/W4399723175","doi":"https://doi.org/10.1145/3665283.3665296"},"language":"en","primary_location":{"id":"doi:10.1145/3665283.3665296","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3665283.3665296","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 24))","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011459117","display_name":"Elias Barbudo","orcid":"https://orcid.org/0000-0002-4557-0678"},"institutions":[{"id":"https://openalex.org/I4210154111","display_name":"Universit\u00e9 Gustave Eiffel","ror":"https://ror.org/03x42jk29","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210154111"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Elias Barbudo","raw_affiliation_strings":["Universit\u00e9 Gustave Eiffel, France"],"raw_orcid":"https://orcid.org/0000-0002-4557-0678","affiliations":[{"raw_affiliation_string":"Universit\u00e9 Gustave Eiffel, France","institution_ids":["https://openalex.org/I4210154111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061712232","display_name":"Thierry Grandpierre","orcid":"https://orcid.org/0000-0002-7239-581X"},"institutions":[{"id":"https://openalex.org/I4210154111","display_name":"Universit\u00e9 Gustave Eiffel","ror":"https://ror.org/03x42jk29","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210154111"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Thierry Grandpierre","raw_affiliation_strings":["Universit\u00e9 Gustave Eiffel, France"],"raw_orcid":"https://orcid.org/0000-0002-7239-581X","affiliations":[{"raw_affiliation_string":"Universit\u00e9 Gustave Eiffel, France","institution_ids":["https://openalex.org/I4210154111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019798129","display_name":"Eva Dokl\u00e1dalov\u00e1","orcid":"https://orcid.org/0000-0003-1765-7394"},"institutions":[{"id":"https://openalex.org/I4210154111","display_name":"Universit\u00e9 Gustave Eiffel","ror":"https://ror.org/03x42jk29","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210154111"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Eva Dokladalova","raw_affiliation_strings":["Universit\u00e9 Gustave Eiffel, France"],"raw_orcid":"https://orcid.org/0000-0003-1765-7394","affiliations":[{"raw_affiliation_string":"Universit\u00e9 Gustave Eiffel, France","institution_ids":["https://openalex.org/I4210154111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06979632,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"133","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8056530952453613},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6824464201927185},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.551731288433075},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.515593945980072},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49977755546569824},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4589492082595825},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3281877040863037},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1742444634437561},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0804082453250885}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8056530952453613},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6824464201927185},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.551731288433075},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.515593945980072},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49977755546569824},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4589492082595825},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3281877040863037},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1742444634437561},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0804082453250885}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3665283.3665296","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3665283.3665296","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 24))","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4000000059604645}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323817","display_name":"Universitas Brawijaya","ror":"https://ror.org/01wk3d929"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1558925342","https://openalex.org/W1986698883","https://openalex.org/W2037725895","https://openalex.org/W2076285066","https://openalex.org/W2945075836"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"focus":[4],"on":[5],"Software":[6],"Programmable":[7],"Streaming":[8],"Coarse-Grained":[9],"Reconfigurable":[10],"Architectures":[11],"(SPS-CGRAs).":[12],"Current":[13],"models":[14],"fail":[15],"to":[16],"capture":[17],"their":[18],"programmability":[19],"and":[20,29,49],"often":[21],"inaccurately":[22],"estimate":[23],"latency":[24,30],"by":[25,54],"ignoring":[26],"configuration":[27,50],"costs":[28],"propagation.":[31],"We":[32],"propose":[33],"a":[34,39],"comprehensive":[35],"modeling":[36],"framework":[37],"using":[38],"graph-based":[40],"hardware":[41],"model":[42],"that":[43],"accounts":[44],"for":[45],"processing,":[46],"memory":[47],"access,":[48],"control,":[51],"all":[52],"parameterized":[53],"latency.":[55]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}